soc.fu package

Subpackages

• soc.fu.alu package
  • Subpackages
    • soc.fu.alu.formal package
      • Submodules
      • soc.fu.alu.formal.proof_input_stage module
      • soc.fu.alu.formal.proof_main_stage module
      • soc.fu.alu.formal.proof_output_stage module
      • Module contents
    • soc.fu.alu.test package
      • Submodules
      • soc.fu.alu.test.svp64_cases module
      • soc.fu.alu.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.alu.alu_input_record module
  • soc.fu.alu.input_stage module
  • soc.fu.alu.main_stage module
  • soc.fu.alu.output_stage module
  • soc.fu.alu.pipe_data module
  • soc.fu.alu.pipeline module
  • Module contents
• soc.fu.branch package
  • Subpackages
    • soc.fu.branch.formal package
      • Submodules
      • soc.fu.branch.formal.proof_input_stage module
      • soc.fu.branch.formal.proof_main_stage module
      • Module contents
    • soc.fu.branch.test package
      • Submodules
      • soc.fu.branch.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.branch.br_input_record module
  • soc.fu.branch.main_stage module
  • soc.fu.branch.pipe_data module
  • soc.fu.branch.pipeline module
  • Module contents
• soc.fu.compunits package
  • Subpackages
    • soc.fu.compunits.formal package
      • Submodules
      • soc.fu.compunits.formal.proof_fu module
      • soc.fu.compunits.formal.test_compunit module
      • Module contents
    • soc.fu.compunits.test package
      • Submodules
      • soc.fu.compunits.test.test_alu_compunit module
      • soc.fu.compunits.test.test_branch_compunit module
      • soc.fu.compunits.test.test_compunit module
      • soc.fu.compunits.test.test_cr_compunit module
      • soc.fu.compunits.test.test_div_compunit module
      • soc.fu.compunits.test.test_ldst_compunit module
      • soc.fu.compunits.test.test_logical_compunit module
      • soc.fu.compunits.test.test_shiftrot_compunit module
      • soc.fu.compunits.test.test_spr_compunit module
      • soc.fu.compunits.test.test_trap_compunit module
      • Module contents
  • Submodules
  • soc.fu.compunits.compunits module
  • Module contents
• soc.fu.cr package
  • Subpackages
    • soc.fu.cr.formal package
      • Submodules
      • soc.fu.cr.formal.proof_main_stage module
      • Module contents
    • soc.fu.cr.test package
      • Submodules
      • soc.fu.cr.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.cr.cr_input_record module
  • soc.fu.cr.main_stage module
  • soc.fu.cr.pipe_data module
  • soc.fu.cr.pipeline module
  • Module contents
• soc.fu.div package
  • Subpackages
    • soc.fu.div.formal package
      • Submodules
      • soc.fu.div.formal.proof_main_stage module
      • Module contents
    • soc.fu.div.test package
      • Submodules
      • soc.fu.div.test.helper module
      • soc.fu.div.test.test_fsm module
      • soc.fu.div.test.test_pipe_caller module
      • soc.fu.div.test.test_pipe_caller_long module
      • soc.fu.div.test.test_pipe_ilang module
      • Module contents
  • Submodules
  • soc.fu.div.core_stages module
  • soc.fu.div.fsm module
  • soc.fu.div.input_stage module
  • soc.fu.div.output_stage module
  • soc.fu.div.pipe_data module
  • soc.fu.div.pipeline module
  • soc.fu.div.setup_stage module
  • soc.fu.div.sim_only_core module
  • Module contents
• soc.fu.ldst package
  • Subpackages
    • soc.fu.ldst.test package
      • Submodules
      • soc.fu.ldst.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.ldst.ldst_input_record module
  • soc.fu.ldst.pipe_data module
  • Module contents
• soc.fu.logical package
  • Subpackages
    • soc.fu.logical.formal package
      • Submodules
      • soc.fu.logical.formal.proof_bpermd module
      • soc.fu.logical.formal.proof_input_stage module
      • soc.fu.logical.formal.proof_main_stage module
      • Module contents
    • soc.fu.logical.test package
      • Submodules
      • soc.fu.logical.test.test_bperm module
      • soc.fu.logical.test.test_countzero module
      • soc.fu.logical.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.logical.bpermd module
  • soc.fu.logical.countzero module
  • soc.fu.logical.input_stage module
  • soc.fu.logical.logical_input_record module
  • soc.fu.logical.main_stage module
  • soc.fu.logical.output_stage module
  • soc.fu.logical.pipe_data module
  • soc.fu.logical.pipeline module
  • soc.fu.logical.popcount module
  • Module contents
• soc.fu.mmu package
  • Subpackages
    • soc.fu.mmu.test package
      • Submodules
      • soc.fu.mmu.test.test_issuer_mmu_data_path module
      • soc.fu.mmu.test.test_non_production_core module
      • soc.fu.mmu.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.mmu.fsm module
  • soc.fu.mmu.mmu_input_record.2 module
  • soc.fu.mmu.mmu_input_record module
  • soc.fu.mmu.pipe_data module
  • Module contents
• soc.fu.mul package
  • Subpackages
    • soc.fu.mul.formal package
      • Submodules
      • soc.fu.mul.formal.proof_main_stage module
      • Module contents
    • soc.fu.mul.test package
      • Submodules
      • soc.fu.mul.test.helper module
      • soc.fu.mul.test.test_pipe_caller module
      • soc.fu.mul.test.test_pipe_caller_long module
      • soc.fu.mul.test.test_pipe_ilang module
      • Module contents
  • Submodules
  • soc.fu.mul.main_stage module
  • soc.fu.mul.mul_input_record module
  • soc.fu.mul.output_stage module
  • soc.fu.mul.pipe_data module
  • soc.fu.mul.pipeline module
  • soc.fu.mul.post_stage module
  • soc.fu.mul.pre_stage module
  • Module contents
• soc.fu.shift_rot package
  • Subpackages
    • soc.fu.shift_rot.formal package
      • Submodules
      • soc.fu.shift_rot.formal.proof_main_stage module
      • Module contents
    • soc.fu.shift_rot.test package
      • Submodules
      • soc.fu.shift_rot.test.test_maskgen module
      • soc.fu.shift_rot.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.shift_rot.input_stage module
  • soc.fu.shift_rot.main_stage module
  • soc.fu.shift_rot.maskgen module
  • soc.fu.shift_rot.output_stage module
  • soc.fu.shift_rot.pipe_data module
  • soc.fu.shift_rot.pipeline module
  • soc.fu.shift_rot.rotator module
  • soc.fu.shift_rot.rotl module
  • soc.fu.shift_rot.sr_input_record module
  • Module contents
• soc.fu.spr package
  • Subpackages
    • soc.fu.spr.formal package
      • Submodules
      • soc.fu.spr.formal.proof_main_stage module
      • Module contents
    • soc.fu.spr.test package
      • Submodules
      • soc.fu.spr.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.spr.main_stage module
  • soc.fu.spr.pipe_data module
  • soc.fu.spr.pipeline module
  • soc.fu.spr.spr_input_record module
  • Module contents
• soc.fu.test package
  • Submodules
  • soc.fu.test.pia module
  • Module contents
• soc.fu.trap package
  • Subpackages
    • soc.fu.trap.formal package
      • Submodules
      • soc.fu.trap.formal.proof_main_stage module
      • Module contents
    • soc.fu.trap.test package
      • Submodules
      • soc.fu.trap.test.test_pipe_caller module
      • Module contents
  • Submodules
  • soc.fu.trap.main_stage module
  • soc.fu.trap.pipe_data module
  • soc.fu.trap.pipeline module
  • soc.fu.trap.trap_input_record module
  • Module contents

Submodules

soc.fu.base_input_record module

class soc.fu.base_input_record.CompOpSubsetBase(layout, name)

Bases: nmigen.hdl.rec.Record

base class of subset Operation information

eq_from(other)

use this to copy in from another CompRecord

eq_from_execute1(other)

use this to copy in from Decode2Execute1Type

ports()

soc.fu.common_input_stage module

class soc.fu.common_input_stage.CommonInputStage(pspec, modname)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)

soc.fu.common_output_stage module

class soc.fu.common_output_stage.CommonOutputStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)

soc.fu.pipe_data module

class soc.fu.pipe_data.CommonPipeSpec(id_wid)

Bases: object

CommonPipeSpec: base class for all pipeline specifications see README.md for explanation of members.

class soc.fu.pipe_data.IntegerData(pspec, output)

Bases: object

IntegerData: base class for all pipeline data structures

see README.md for explanation of parameters and purpose.

note the mode parameter - output. XXXInputData specs must have this set to “False”, and XXXOutputData specs (and anything that creates intermediary outputs which propagate through a pipeline to output) must have it set to “True”.

eq(i)

ports()

soc.fu.pipe_data.get_rec_width(rec)

soc.fu.regspec module

RegSpecs

see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs

this module is a key strategic module that links pipeline specifications (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits. MultiCompUnits know absolutely nothing about the data passing through them: all they know is: how many inputs they need to manage, and how many outputs.

regspecs tell MultiCompUnit what the ordering of the inputs is, how many to create, and how to connect them up to the ALU being “managed” by this CompUnit. likewise for outputs.

later (TODO) the Register Files will be connected to MultiCompUnits, and, again, the regspecs will say which Regfile (which type) is connected to which MultiCompUnit port, how wide the connection is, and so on.

class soc.fu.regspec.RegSpec(rwid, n_src=None, n_dst=None, name=None)

Bases: object

class soc.fu.regspec.RegSpecALUAPI(rwid, alu)

Bases: soc.fu.regspec.RegSpecAPI

get_in(i)

get_op()

get_out(i)

class soc.fu.regspec.RegSpecAPI(rwid)

Bases: object

get_in_name(i)

get_in_spec(i)

get_out_name(i)

get_out_spec(i)

soc.fu.regspec.get_regspec_bitwidth(regspec, srcdest, idx)

Module contents