soc.fu.logical package

Submodules

soc.fu.logical.bpermd module

class soc.fu.logical.bpermd.Bpermd(width)

Bases: nmigen.hdl.ir.Elaboratable

from POWERISA v3.1 p105, chaper 3

This class does a Bit Permute on a Doubleword

permd RA,RS,RB

do i = 0 to 7

index ← (RS)[8*i:8*i+7] If index < 64

then perm[i] ← (RB)[index] else permi[i] ← 0

RA ←56[0] || perm[0:7]

Eight permuted bits are produced. For each permutedbit i where i ranges from 0 to 7 and for each byte i of RS, do the following.

If byte i of RS is less than 64, permuted bit i is set to the bit of RB specified by byte i of RS; otherwise permuted bit i is set to 0.

The permuted bits are placed in the least-significant byte of RA, and the remaining bits are filled with 0s.

Special Registers Altered:
None

Programming Note:

The fact that the permuted bit is 0 if the corresponding index value exceeds 63 permits the permuted bits to be selected from a 128-bit quantity, using a single index register. For example, assume that the 128-bit quantity Q, from which the permuted bits are to be selected, is in registers r2 (high-order 64 bits of Q) and r3 (low-order 64 bits of Q), that the index values are in register r1, with each byte of r1 containing a value in the range 0:127, and that each byte of register r4 contains the value 64. The following code sequence selects eight permuted bits from Q and places them into the low-order byteof r6.

bpermd r6,r1,r2 # select from high-order half of Q xor r0,r1,r4 # adjust index values bpermd r5,r0,r3 # select from low-order half of Q or r6,r6,r5 # merge the two selections

elaborate(platform)

soc.fu.logical.countzero module

class soc.fu.logical.countzero.IntermediateResult(name=None)

Bases: nmigen.hdl.rec.Record

class soc.fu.logical.countzero.ZeroCounter

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
ports()
soc.fu.logical.countzero.or4(a, b, c, d)

soc.fu.logical.input_stage module

class soc.fu.logical.input_stage.LogicalInputStage(pspec)

Bases: soc.fu.common_input_stage.CommonInputStage

elaborate(platform)
ispec()
ospec()

soc.fu.logical.logical_input_record module

class soc.fu.logical.logical_input_record.CompLogicalOpSubset(name=None)

Bases: soc.fu.base_input_record.CompOpSubsetBase

a copy of the relevant subset information from Decode2Execute1Type needed for Logical operations. use with eq_from_execute1 (below) to grab subsets.

soc.fu.logical.main_stage module

class soc.fu.logical.main_stage.LogicalMainStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)
ispec()
ospec()

soc.fu.logical.output_stage module

class soc.fu.logical.output_stage.LogicalOutputStage(pspec)

Bases: soc.fu.common_output_stage.CommonOutputStage

ispec()
ospec()

soc.fu.logical.pipe_data module

class soc.fu.logical.pipe_data.LogicalInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('XER', 'xer_so', '32')]
class soc.fu.logical.pipe_data.LogicalOutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_so', '32')]
class soc.fu.logical.pipe_data.LogicalOutputDataFinal(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3')]
class soc.fu.logical.pipe_data.LogicalPipeSpec(id_wid)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.logical.logical_input_record.CompLogicalOpSubset

regspec = ([('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('XER', 'xer_so', '32')], [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3')])

soc.fu.logical.pipeline module

class soc.fu.logical.pipeline.LogicalBasePipe(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class soc.fu.logical.pipeline.LogicalStages1(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()
class soc.fu.logical.pipeline.LogicalStages2(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

soc.fu.logical.popcount module

Popcount: a successive (cascading) sum-reduction algorithm for counting bits

starting from single-bit adds and reducing down to one final answer: the total number of bits set to “1” in the input.

unfortunately there is a bit of a “trick” going on which you have to watch out for: whilst the first list added to pc is a single entry (the input, a), subsequent rows in the cascade are arrays of partial results, yet it turns out that referring to them using the exact same start/end slicing is perfect. this comes down to nmigen’s transparent use of python features to make Signals iterable.

class soc.fu.logical.popcount.Popcount

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
soc.fu.logical.popcount.array_of(count, bitwidth)

Module contents