soc.fu.div.test package

Submodules

soc.fu.div.test.helper module

class soc.fu.div.test.helper.DivTestHelper(methodName='runTest')

Bases: unittest.case.TestCase

check_alu_outputs(alu, dec2, sim, code, pia_res)

execute(alu, instruction, pdecode2, test, div_pipe_kind, sim)

run_all(test_data, div_pipe_kind, file_name_prefix)

soc.fu.div.test.helper.get_cu_inputs(dec2, sim)

naming (res) must conform to DivFunctionUnit input regspec

soc.fu.div.test.helper.log_rand(n, min_val=1)

soc.fu.div.test.helper.set_alu_inputs(alu, dec2, sim)

soc.fu.div.test.test_fsm module

class soc.fu.div.test.test_fsm.CheckEvent

Bases: nmigen.hdl.ir.Elaboratable

helper to add indication to vcd when signals are checked

elaborate(platform)

trigger()

class soc.fu.div.test.test_fsm.DivStateCombTest(quotient_width)

Bases: nmigen.hdl.ir.Elaboratable

Test stringing a bunch of copies of the FSM state-function together

elaborate(platform)

class soc.fu.div.test.test_fsm.DivStateFSMTest(quotient_width)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

class soc.fu.div.test.test_fsm.TestDivState(methodName='runTest')

Bases: unittest.case.TestCase

test_div_state_comb(quotient_width=8)

test_div_state_fsm(quotient_width=8)

soc.fu.div.test.test_fsm.get_cases(quotient_width)

soc.fu.div.test.test_pipe_caller module

class soc.fu.div.test.test_pipe_caller.TestPipe(methodName='runTest')

Bases: soc.fu.div.test.helper.DivTestHelper

test_div_pipe_core()

test_fsm_div_core()

test_sim_only()

soc.fu.div.test.test_pipe_caller_long module

class soc.fu.div.test.test_pipe_caller_long.TestPipeLong(methodName='runTest')

Bases: soc.fu.div.test.helper.DivTestHelper

test_div_pipe_core()

test_fsm_div_core()

test_sim_only()

soc.fu.div.test.test_pipe_ilang module

class soc.fu.div.test.test_pipe_ilang.TestPipeIlang(methodName='runTest')

Bases: unittest.case.TestCase

test_div_pipe_core()

test_fsm_div_core()

test_sim_only()

write_ilang(div_pipe_kind)

Module contents