soc.fu.trap package

Subpackages

• soc.fu.trap.formal package
  • Submodules
  • soc.fu.trap.formal.proof_main_stage module
  • Module contents
• soc.fu.trap.test package
  • Submodules
  • soc.fu.trap.test.test_pipe_caller module
  • Module contents

Submodules

soc.fu.trap.main_stage module

Trap Pipeline

Deals with td/tw/tdi/twi as well as mfmsr/mtmsr, sc and rfid. addpcis TODO. Also used generally for interrupts (as a micro-coding mechanism) by actually modifying the decoded instruction in PowerDecode2.

• https://bugs.libre-soc.org/show_bug.cgi?id=325
• https://bugs.libre-soc.org/show_bug.cgi?id=344
• https://libre-soc.org/openpower/isa/fixedtrap/

class soc.fu.trap.main_stage.TrapMainStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)

ispec()

msr_exception(m, trap_addr, msr_hv=None)

msr_exception - sets bits in MSR specific to an exception. the full list of what needs to be done is given in V3.0B Book III Section 6.5 p1063 however it turns out that for the majority of cases (microwatt showing the way, here), all these bits are all set by all (implemented) interrupt types. this may change in the future, hence the (unused) trap_addr argument

ospec()

trap(m, trap_addr, return_addr)

trap. sets new PC, stores MSR and old PC in SRR1 and SRR0

soc.fu.trap.main_stage.msr_check_pr(m, msr)

msr_check_pr: checks “problem state”

soc.fu.trap.main_stage.msr_copy(msr_o, msr_i, zero_me=True)

ISA says this: Defined MSR bits are classified as either full func tion or partial function. Full function MSR bits are saved in SRR1 or HSRR1 when an interrupt other than a System Call Vectored interrupt occurs and restored by rfscv, rfid, or hrfid, while partial function MSR bits are not saved or restored. Full function MSR bits lie in the range 0:32, 37:41, and 48:63, and partial function MSR bits lie in the range 33:36 and 42:47. (Note this is IBM bit numbering).

soc.fu.trap.pipe_data module

class soc.fu.trap.pipe_data.TrapInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63')]

class soc.fu.trap.pipe_data.TrapOutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('STATE', 'nia', '0:63'), ('STATE', 'msr', '0:63')]

class soc.fu.trap.pipe_data.TrapPipeSpec(id_wid)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.trap.trap_input_record.CompTrapOpSubset

regspec = ([('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63')], [('INT', 'o', '0:63'), ('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('STATE', 'nia', '0:63'), ('STATE', 'msr', '0:63')])

soc.fu.trap.pipeline module

class soc.fu.trap.pipeline.DummyTrapStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)

ispec()

ospec()

class soc.fu.trap.pipeline.TrapBasePipe(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class soc.fu.trap.pipeline.TrapDummyStages(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

class soc.fu.trap.pipeline.TrapStages(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

soc.fu.trap.trap_input_record module

class soc.fu.trap.trap_input_record.CompTrapOpSubset(name=None)

Bases: soc.fu.base_input_record.CompOpSubsetBase

a copy of the relevant subset information from Decode2Execute1Type needed for TRAP operations. use with eq_from_execute1 (below) to grab subsets.

Module contents