soc.fu.mmu package

Subpackages

• soc.fu.mmu.test package
  • Submodules
  • soc.fu.mmu.test.test_issuer_mmu_data_path module
  • soc.fu.mmu.test.test_non_production_core module
  • soc.fu.mmu.test.test_pipe_caller module
  • Module contents

Submodules

soc.fu.mmu.fsm module

class soc.fu.mmu.fsm.FSMMMUStage(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

ports()

class soc.fu.mmu.fsm.LoadStore1(regwid=64, addrwid=4)

Bases: soc.experiment.pimem.PortInterfaceBase

elaborate(platform)

get_rd_data(m)

ports()

set_rd_addr(m, addr, mask)

set_wr_addr(m, addr, mask)

set_wr_data(m, data, wen)

soc.fu.mmu.mmu_input_record.2 module

soc.fu.mmu.mmu_input_record module

class soc.fu.mmu.mmu_input_record.CompMMUOpSubset(name=None)

Bases: soc.fu.base_input_record.CompOpSubsetBase

a copy of the relevant subset information from Decode2Execute1Type needed for MMU operations. use with eq_from_execute1 (below) to grab subsets.

soc.fu.mmu.pipe_data module

MMU Pipeline Data structures

Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.

Interestingly none of the MMU instructions use RA, they all use RB. except dcbz which uses (RA|0)

Links: * https://bugs.libre-soc.org/show_bug.cgi?id=491 * https://libre-soc.org/3d_gpu/architecture/regfile/

class soc.fu.mmu.pipe_data.MMUInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('SPR', 'spr1', '0:63')]

class soc.fu.mmu.pipe_data.MMUOutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('SPR', 'spr1', '0:63')]

class soc.fu.mmu.pipe_data.MMUPipeSpec(id_wid)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.mmu.mmu_input_record.CompMMUOpSubset

regspec = ([('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('SPR', 'spr1', '0:63')], [('INT', 'o', '0:63'), ('SPR', 'spr1', '0:63')])

Module contents