soc.fu.shift_rot package

Submodules

soc.fu.shift_rot.input_stage module

class soc.fu.shift_rot.input_stage.ShiftRotInputStage(pspec)

Bases: soc.fu.common_input_stage.CommonInputStage

elaborate(platform)
ispec()
ospec()

soc.fu.shift_rot.main_stage module

class soc.fu.shift_rot.main_stage.ShiftRotMainStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)
ispec()
ospec()

soc.fu.shift_rot.maskgen module

class soc.fu.shift_rot.maskgen.MaskGen(width)

Bases: nmigen.hdl.ir.Elaboratable

MaskGen - create a diff mask

example: x=5 –> a=0b11111
y=3 –> b=0b00111 o: 0b11000 x=2 –> a=0b00011 y=4 –> b=0b01111 o: 0b10011
elaborate(platform)
ports()

soc.fu.shift_rot.output_stage module

class soc.fu.shift_rot.output_stage.ShiftRotOutputStage(pspec)

Bases: soc.fu.common_output_stage.CommonOutputStage

ispec()
ospec()

soc.fu.shift_rot.pipe_data module

class soc.fu.shift_rot.pipe_data.ShiftRotInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('INT', 'rc', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ca', '34,45')]
class soc.fu.shift_rot.pipe_data.ShiftRotOutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_so', '32'), ('XER', 'xer_ca', '34,45')]
class soc.fu.shift_rot.pipe_data.ShiftRotOutputDataFinal(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45')]
class soc.fu.shift_rot.pipe_data.ShiftRotPipeSpec(id_wid)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.shift_rot.sr_input_record.CompSROpSubset

regspec = ([('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('INT', 'rc', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ca', '34,45')], [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45')])

soc.fu.shift_rot.pipeline module

class soc.fu.shift_rot.pipeline.ShiftRotBasePipe(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class soc.fu.shift_rot.pipeline.ShiftRotStageEnd(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()
class soc.fu.shift_rot.pipeline.ShiftRotStages(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

soc.fu.shift_rot.rotator module

class soc.fu.shift_rot.rotator.Rotator

Bases: nmigen.hdl.ir.Elaboratable

Rotator: covers multiple POWER9 rotate functions

supported modes:

  • sl[wd]
  • rlw*, rldic, rldicr, rldimi
  • rldicl, sr[wd]
  • sra[wd][i]

use as follows:

  • shift = RB[0:7]
  • arith = 1 when is_signed
  • right_shift = 1 when insn_type is OP_SHR
  • clear_left = 1 when insn_type is OP_RLC or OP_RLCL
  • clear_right = 1 when insn_type is OP_RLC or OP_RLCR
elaborate(platform)
soc.fu.shift_rot.rotator.left_mask(m, mask_end)
soc.fu.shift_rot.rotator.right_mask(m, mask_begin)

soc.fu.shift_rot.rotl module

class soc.fu.shift_rot.rotl.ROTL(width)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

soc.fu.shift_rot.sr_input_record module

class soc.fu.shift_rot.sr_input_record.CompSROpSubset(name=None)

Bases: soc.fu.base_input_record.CompOpSubsetBase

a copy of the relevant subset information from Decode2Execute1Type needed for ALU operations. use with eq_from_execute1 (below) to grab subsets.

Module contents