soc.fu.div package

Submodules

soc.fu.div.core_stages module

class soc.fu.div.core_stages.DivCoreBaseStage(pspec, modname, core_class, *args, **kwargs)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)
class soc.fu.div.core_stages.DivCoreSetupStage(pspec)

Bases: soc.fu.div.core_stages.DivCoreBaseStage

ispec()
ospec()
class soc.fu.div.core_stages.DivCoreCalculateStage(pspec, stage_index)

Bases: soc.fu.div.core_stages.DivCoreBaseStage

ispec()
ospec()
class soc.fu.div.core_stages.DivCoreFinalStage(pspec)

Bases: soc.fu.div.core_stages.DivCoreBaseStage

ispec()
ospec()

soc.fu.div.fsm module

class soc.fu.div.fsm.DivState(quotient_width, name)

Bases: object

done
eq(rhs)
quotient

get the quotient – requires self.done is True

remainder

get the remainder – requires self.done is True

will_be_done_after(steps)

Returns 1 if this state will be done after another steps passes through DivStateNext.

class soc.fu.div.fsm.DivStateInit(quotient_width)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
class soc.fu.div.fsm.DivStateNext(quotient_width)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
class soc.fu.div.fsm.FSMDivCoreConfig

Bases: object

bit_width = 64
fract_width = 64
n_stages = 1
class soc.fu.div.fsm.FSMDivCoreInputData(core_config, reset_less=True)

Bases: object

eq(rhs)

Assign member signals.

class soc.fu.div.fsm.FSMDivCoreOutputData(core_config, reset_less=True)

Bases: object

eq(rhs)

Assign member signals.

class soc.fu.div.fsm.FSMDivCoreStage(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

ports()

soc.fu.div.input_stage module

class soc.fu.div.input_stage.DivMulInputStage(pspec)

Bases: soc.fu.alu.input_stage.ALUInputStage

ispec()
ospec()

soc.fu.div.output_stage module

class soc.fu.div.output_stage.DivOutputStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)
ispec()
ospec()

soc.fu.div.pipe_data module

class soc.fu.div.pipe_data.CoreBaseData(pspec, core_data_class)

Bases: soc.fu.div.pipe_data.DivInputData

eq(rhs)
eq_without_core(rhs)
class soc.fu.div.pipe_data.CoreInputData(pspec)

Bases: soc.fu.div.pipe_data.CoreBaseData

class soc.fu.div.pipe_data.CoreInterstageData(pspec)

Bases: soc.fu.div.pipe_data.CoreBaseData

class soc.fu.div.pipe_data.CoreOutputData(pspec)

Bases: soc.fu.div.pipe_data.CoreBaseData

class soc.fu.div.pipe_data.DivInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('XER', 'xer_so', '32')]
class soc.fu.div.pipe_data.DivMulOutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_so', '32')]
class soc.fu.div.pipe_data.DivPipeKind

Bases: enum.Enum

An enumeration.

DivPipeCore = 1
FSMDivCore = 3
SimOnly = 2
class soc.fu.div.pipe_data.DivPipeKindConfigBase(core_config, core_input_data_class, core_interstage_data_class, core_output_data_class)

Bases: object

class soc.fu.div.pipe_data.DivPipeKindConfigCombPipe(core_config, core_input_data_class, core_interstage_data_class, core_output_data_class, core_setup_stage_class, core_calculate_stage_class, core_final_stage_class)

Bases: soc.fu.div.pipe_data.DivPipeKindConfigBase

class soc.fu.div.pipe_data.DivPipeKindConfigFSM(core_config, core_input_data_class, core_output_data_class, core_stage_class)

Bases: soc.fu.div.pipe_data.DivPipeKindConfigBase

class soc.fu.div.pipe_data.DivPipeSpec(id_wid, div_pipe_kind)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.logical.logical_input_record.CompLogicalOpSubset

regspec = ([('INT', 'ra', '0:63'), ('INT', 'rb', '0:63'), ('XER', 'xer_so', '32')], [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_so', '32')])
class soc.fu.div.pipe_data.DivPipeSpecDivPipeCore(id_wid)

Bases: soc.fu.div.pipe_data.DivPipeSpec

class soc.fu.div.pipe_data.DivPipeSpecFSMDivCore(id_wid)

Bases: soc.fu.div.pipe_data.DivPipeSpec

class soc.fu.div.pipe_data.DivPipeSpecSimOnly(id_wid)

Bases: soc.fu.div.pipe_data.DivPipeSpec

soc.fu.div.pipeline module

class soc.fu.div.pipeline.DivBasePipe(pspec, compute_steps_per_stage=4)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class soc.fu.div.pipeline.DivStagesEnd(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()
class soc.fu.div.pipeline.DivStagesMiddle(pspec, stage_start_index, stage_end_index)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()
class soc.fu.div.pipeline.DivStagesStart(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

soc.fu.div.setup_stage module

class soc.fu.div.setup_stage.DivSetupStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)
ispec()
ospec()

soc.fu.div.sim_only_core module

class soc.fu.div.sim_only_core.SimOnlyCoreCalculateStage(core_config, stage_index)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

Elaborate into Module.

ispec()

Get the input spec for this pipeline stage.

ospec()

Get the output spec for this pipeline stage.

process(i)

Pipeline stage process.

setup(m, i)

Pipeline stage setup.

class soc.fu.div.sim_only_core.SimOnlyCoreConfig

Bases: object

bit_width = 64
fract_width = 64
n_stages = 1
class soc.fu.div.sim_only_core.SimOnlyCoreFinalStage(core_config)

Bases: nmigen.hdl.ir.Elaboratable

Final Stage of the core of the div/rem/sqrt/rsqrt pipeline.

elaborate(platform)

Elaborate into Module.

ispec()

Get the input spec for this pipeline stage.

ospec()

Get the output spec for this pipeline stage.

process(i)

Pipeline stage process.

setup(m, i)

Pipeline stage setup.

class soc.fu.div.sim_only_core.SimOnlyCoreInputData(core_config, reset_less=True)

Bases: object

eq(rhs)

Assign member signals.

class soc.fu.div.sim_only_core.SimOnlyCoreInterstageData(core_config, reset_less=True)

Bases: object

eq(rhs)

Assign member signals.

class soc.fu.div.sim_only_core.SimOnlyCoreOutputData(core_config, reset_less=True)

Bases: object

eq(rhs)

Assign member signals.

class soc.fu.div.sim_only_core.SimOnlyCoreSetupStage(core_config)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

Elaborate into Module.

ispec()

Get the input spec for this pipeline stage.

ospec()

Get the output spec for this pipeline stage.

process(i)

Pipeline stage process.

setup(m, i)

Pipeline stage setup.

Module contents