soc.fu.branch package

Subpackages

• soc.fu.branch.formal package
  • Submodules
  • soc.fu.branch.formal.proof_input_stage module
  • soc.fu.branch.formal.proof_main_stage module
  • Module contents
• soc.fu.branch.test package
  • Submodules
  • soc.fu.branch.test.test_pipe_caller module
  • Module contents

Submodules

soc.fu.branch.br_input_record module

class soc.fu.branch.br_input_record.CompBROpSubset(name=None)

Bases: soc.fu.base_input_record.CompOpSubsetBase

a copy of the relevant subset information from Decode2Execute1Type needed for Branch operations. use with eq_from_execute1 (below) to grab subsets.

soc.fu.branch.main_stage module

Branch Pipeline

This stage is intended to do most of the work of executing branch instructions. This is OP_B, OP_B, OP_BCREG

Note: it is PARTICULARLY important to pay attention to PowerDecode2 more specifically DecodeRA etc. as these work closely in conjunction with the Branch pipeline, here.

The Branch pipeline itself does not and cannot read registers: it can only process data and produce results. Therefore, something else needs to know that BC needs CTR, and that one of the outputs from here is to go into LR, and so on. Encoding of which registers are read and written is the responsibility of PowerDecode2 and because some of those decisions are conditional (based on BO2 for example) PowerDecode2 has to duplicate some of that bitlevel operand field decoding.

It us therefore quite critical to read this code in conjunction side by side with power_decode2.py

Links: * https://bugs.libre-soc.org/show_bug.cgi?id=313 * https://bugs.libre-soc.org/show_bug.cgi?id=335 * https://libre-soc.org/openpower/isa/branch/

class soc.fu.branch.main_stage.BranchMainStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)

ispec()

ospec()

soc.fu.branch.main_stage.br_ext(bd)

computes sign-extended NIA (assumes word-alignment)

soc.fu.branch.pipe_data module

Optional Register allocation listed below. mandatory input (CompBROpSubset, CIA) not included.

• CR is Condition Register (not an SPR)
• SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed

insn CR SPR2 SPR1 —- – —- —- op_b xx xx xx op_ba xx xx xx op_bl xx xx xx op_bla xx xx xx op_bc CR, xx, CTR op_bca CR, xx, CTR op_bcl CR, xx, CTR op_bcla CR, xx, CTR op_bclr CR, LR, CTR op_bclrl CR, LR, CTR op_bcctr CR, xx, CTR op_bcctrl CR, xx, CTR op_bctar CR, TAR, CTR op_bctarl CR, TAR, CTR

class soc.fu.branch.pipe_data.BranchInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('CR', 'cr_a', '0:3')]

class soc.fu.branch.pipe_data.BranchOutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('STATE', 'nia', '0:63')]

class soc.fu.branch.pipe_data.BranchPipeSpec(id_wid)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.branch.br_input_record.CompBROpSubset

regspec = ([('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('CR', 'cr_a', '0:3')], [('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('STATE', 'nia', '0:63')])

soc.fu.branch.pipeline module

class soc.fu.branch.pipeline.BranchBasePipe(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class soc.fu.branch.pipeline.BranchStages(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

Module contents