soc.fu.compunits package

Subpackages

• soc.fu.compunits.formal package
  • Submodules
  • soc.fu.compunits.formal.proof_fu module
  • soc.fu.compunits.formal.test_compunit module
  • Module contents
• soc.fu.compunits.test package
  • Submodules
  • soc.fu.compunits.test.test_alu_compunit module
  • soc.fu.compunits.test.test_branch_compunit module
  • soc.fu.compunits.test.test_compunit module
  • soc.fu.compunits.test.test_cr_compunit module
  • soc.fu.compunits.test.test_div_compunit module
  • soc.fu.compunits.test.test_ldst_compunit module
  • soc.fu.compunits.test.test_logical_compunit module
  • soc.fu.compunits.test.test_shiftrot_compunit module
  • soc.fu.compunits.test.test_spr_compunit module
  • soc.fu.compunits.test.test_trap_compunit module
  • Module contents

Submodules

soc.fu.compunits.compunits module

Function Units Construction

This module pulls all of the pipelines together (soc.fu.*) and, using the regspec and Computation Unit APIs, constructs Scoreboard-aware Function Units that may systematically and automatically be wired up to appropriate Register Files.

Two types exist:

• Single-cycle Function Units. these are FUs that will only block for one cycle. it is expected that multiple of these be instantiated, because they are simple and trivial, and not many gates.
  • ALU, Logical: definitely several
  • CR: not so many needed (perhaps)
  • Branch: one or two of these (depending on speculation run-ahead)
  • Trap: yeah really only one of these
  • SPR: again, only one.
  • ShiftRot (perhaps not too many of these)
• Multi-cycle (and FSM) Function Units. these are FUs that can only handle a limited number of values, and take several cycles to complete. Given that under Scoreboard Management, start and completion must be fully managed, a “Reservation Station” style approach is required: one multiple-stage (N stage) pipelines need a minimum of N (plural) “CompUnit” front-ends. this includes:
  • MUL (all versions including MAC)
  • DIV (including modulo)

In either case, there will be multiple MultiCompUnits: it’s just that single-cycle ones are instantiated individually (one single-cycle pipeline per MultiCompUnit, and multi-cycle ones need to be instantiated en-masse, where only one actual pipeline (or FSM) has multiple Reservation Stations.

see:

• https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs

class soc.fu.compunits.compunits.ALUFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 2

class soc.fu.compunits.compunits.AllFunctionUnits(pspec, pilist=None, div_fsm=True)

Bases: nmigen.hdl.ir.Elaboratable

creates a dictionary of Function Units according to required spec. tuple is of:

• name of ALU,
• quantity of FUs required
• type of FU required

elaborate(platform)

ports()

class soc.fu.compunits.compunits.BranchFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 32

class soc.fu.compunits.compunits.CRFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 64

class soc.fu.compunits.compunits.DivFSMFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 512

class soc.fu.compunits.compunits.DivPipeFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 512

class soc.fu.compunits.compunits.FunctionUnitBaseMulti

Bases: object

class soc.fu.compunits.compunits.FunctionUnitBaseSingle(speckls, pipekls, idx)

Bases: soc.experiment.compalu_multi.MultiCompUnit

main “glue” class that brings everything together. ONLY use this class for single-stage pipelines.

• speckls:

  • the specification. contains regspec and op subset info,

  and contains common “stuff” like the pipeline ctx, what type of nmutil pipeline base is to be used (etc)

• pipekls:

  • the type of pipeline. actually connects things together

note that it is through MultiCompUnit.get_in/out that we actually connect up the association between regspec variable names (defined in the pipe_data).

note that the rdflags function obtains (dynamically, from instruction decoding) which read-register ports are to be requested. this is not ideal (it could be a lot neater) but works for now.

class soc.fu.compunits.compunits.LDSTFunctionUnit(pi, awid, idx)

Bases: soc.experiment.compldst_multi.LDSTCompUnit

fnunit = 4

class soc.fu.compunits.compunits.LogicalFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 16

class soc.fu.compunits.compunits.MMUFSMFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 2048

class soc.fu.compunits.compunits.MulFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 256

class soc.fu.compunits.compunits.SPRFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 1024

class soc.fu.compunits.compunits.ShiftRotFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 8

class soc.fu.compunits.compunits.TrapFunctionUnit(idx)

Bases: soc.fu.compunits.compunits.FunctionUnitBaseSingle

fnunit = 128

soc.fu.compunits.compunits.tst_all_fus()

soc.fu.compunits.compunits.tst_single_fus_il()

Module contents