soc.fu.spr package

Subpackages

• soc.fu.spr.formal package
  • Submodules
  • soc.fu.spr.formal.proof_main_stage module
  • Module contents
• soc.fu.spr.test package
  • Submodules
  • soc.fu.spr.test.test_pipe_caller module
  • Module contents

Submodules

soc.fu.spr.main_stage module

SPR Pipeline

• https://bugs.libre-soc.org/show_bug.cgi?id=348
• https://libre-soc.org/openpower/isa/sprset/

class soc.fu.spr.main_stage.SPRMainStage(pspec)

Bases: nmutil.pipemodbase.PipeModBase

elaborate(platform)

ispec()

ospec()

soc.fu.spr.pipe_data module

SPR Pipeline Data structures

Covers MFSPR and MTSPR. however given that the SPRs are split across XER (which is 3 separate registers), Fast-SPR and Slow-SPR regfiles, the data structures are slightly more involved than just “INT, SPR”.

Links: * https://bugs.libre-soc.org/show_bug.cgi?id=348 * https://libre-soc.org/openpower/isa/sprset/ * https://libre-soc.org/3d_gpu/architecture/regfile/

class soc.fu.spr.pipe_data.SPRInputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'ra', '0:63'), ('SPR', 'spr1', '0:63'), ('FAST', 'fast1', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_ca', '34,45')]

class soc.fu.spr.pipe_data.SPROutputData(pspec)

Bases: soc.fu.pipe_data.IntegerData

regspec = [('INT', 'o', '0:63'), ('SPR', 'spr1', '0:63'), ('FAST', 'fast1', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_ca', '34,45')]

class soc.fu.spr.pipe_data.SPRPipeSpec(id_wid)

Bases: soc.fu.pipe_data.CommonPipeSpec

opsubsetkls

alias of soc.fu.spr.spr_input_record.CompSPROpSubset

regspec = ([('INT', 'ra', '0:63'), ('SPR', 'spr1', '0:63'), ('FAST', 'fast1', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_ca', '34,45')], [('INT', 'o', '0:63'), ('SPR', 'spr1', '0:63'), ('FAST', 'fast1', '0:63'), ('XER', 'xer_so', '32'), ('XER', 'xer_ov', '33,44'), ('XER', 'xer_ca', '34,45')])

soc.fu.spr.pipeline module

class soc.fu.spr.pipeline.SPRBasePipe(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class soc.fu.spr.pipeline.SPRStages(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

soc.fu.spr.spr_input_record module

class soc.fu.spr.spr_input_record.CompSPROpSubset(name=None)

Bases: soc.fu.base_input_record.CompOpSubsetBase

a copy of the relevant subset information from Decode2Execute1Type needed for TRAP operations. use with eq_from_execute1 (below) to grab subsets.

Module contents