openpower package

Subpackages

Submodules

openpower.consts module

class openpower.consts.CR

Bases: object

EQ = 1
GT = 2
LT = 3
SO = 0
class openpower.consts.CRb

Bases: object

EQ = 2
GT = 1
LT = 0
SO = 3
class openpower.consts.EXTRA2

Bases: object

IDX0_MSB = 7
IDX0_VEC = 8
IDX1_MSB = 5
IDX1_VEC = 6
IDX2_MSB = 3
IDX2_VEC = 4
IDX3_MSB = 1
IDX3_VEC = 2
RESERVED = 0
class openpower.consts.EXTRA2b

Bases: object

IDX0_MSB = 1
IDX0_VEC = 0
IDX1_MSB = 3
IDX1_VEC = 2
IDX2_MSB = 5
IDX2_VEC = 4
IDX3_MSB = 7
IDX3_VEC = 6
RESERVED = 8
class openpower.consts.EXTRA3

Bases: object

IDX0 = [0, 1, 2]
IDX1 = [3, 4, 5]
IDX2 = [6, 7, 8]
MASK = [6, 7, 8]
class openpower.consts.FastRegsEnum

Bases: object

CTR = 0
DEC = 6
LR = 1
N_REGS = 9
SRR0 = 3
SRR1 = 4
SVSRR0 = 8
TAR = 2
TB = 7
XER = 5
class openpower.consts.MSR

Bases: object

DR = 4
EE = 15
FE0 = 11
FE1 = 8
FP = 13
HV = 60
IR = 5
LE = 0
ME = 12
PMM = 3
PR = 14
RI = 1
S = 22
SF = 63
TEe = 9
TEs = 10
TM = 32
TSe = 33
TSs = 34
UND = 58
VEC = 25
VSX = 23
class openpower.consts.MSRb

Bases: object

DR = 59
EE = 48
FE0 = 52
FE1 = 55
FP = 50
HV = 3
IR = 58
LE = 63
ME = 51
PMM = 60
PR = 49
RI = 62
S = 41
SF = 0
TEe = 54
TEs = 53
TM = 31
TSe = 30
TSs = 29
UND = 5
VEC = 38
VSX = 40
class openpower.consts.PI

Bases: object

ADR = 16
FP = 20
ILLEG = 19
INVALID = 30
PERMERR = 28
PRIV = 18
TM_BAD_THING = 21
TRAP = 17
class openpower.consts.PIb

Bases: object

ADR = 47
FP = 43
ILLEG = 44
INVALID = 33
PERMERR = 35
PRIV = 45
TM_BAD_THING = 42
TRAP = 46
class openpower.consts.SPEC

Bases: object

LSB = 0
MSB = 1
VEC = 2
class openpower.consts.SPECb

Bases: object

LSB = 2
MSB = 1
VEC = 0
class openpower.consts.SVP64CROffs

Bases: object

CR0 = 0
CR1 = 1
CRPred = 4
class openpower.consts.SVP64MODE

Bases: object

BO_LSB = 0
BO_MSB = 2
CR = [3, 4]
CRM = 0
CR_LSB = 0
CR_MSB = 1
DZ = 1
ELS_FFIRST_PRED = 1
ELS_NORMAL = 2
ELS_SAT = 0
INV = 2
MOD2 = [0, 1]
MOD2_LSB = 3
MOD2_MSB = 4
N = 2
RC1 = 0
REDUCE = 2
SVM = 1
SZ = 0
class openpower.consts.SVP64MODEb

Bases: object

BO_LSB = 4
BO_MSB = 2
CRM = 4
CR_LSB = 4
CR_MSB = 3
DZ = 3
ELS_FFIRST_PRED = 3
ELS_NORMAL = 2
ELS_SAT = 4
INV = 2
MOD2_LSB = 1
MOD2_MSB = 0
N = 2
RC1 = 4
REDUCE = 2
SVM = 3
SZ = 4
class openpower.consts.SVP64P

Bases: object

OPC = range(0, 6)
RM = [6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
SVP64_7_9 = [7, 9]
class openpower.consts.StateRegsEnum

Bases: object

MSR = 1
N_REGS = 3
PC = 0
SVSTATE = 2
class openpower.consts.TT

Bases: object

ADDR = 8
DEC = 32
EINT = 16
FP = 1
ILLEG = 128
MEMEXC = 64
PRIV = 2
TRAP = 4
size = 8
class openpower.consts.XERRegsEnum

Bases: object

CA = 1
N_REGS = 3
OV = 2
SO = 0
openpower.consts.botchify(bekls, lekls, msb=63)
openpower.consts.field(r, msb0_start, msb0_end=None, field_width=64)

Answers with a subfield of the signal r (“register”), where the start and end bits use IBM conventions. start < end, if end is provided. The range specified is inclusive on both ends.

Answers with a subfield of the signal r (“register”), where the start and end bits use IBM “MSB 0” conventions. If end is not provided, a single bit subfield is returned.

see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering

  • assertion: msb0_start < msb0_end.
  • The range specified is inclusive on both ends.
  • field_width specifies the total number of bits (note: not bits-1)

Example usage:

comb += field(insn, 0, 6, field_width=32).eq(17) # NOTE: NEVER DIRECTLY ACCESS OPCODE FIELDS IN INSTRUCTIONS. # This example is purely for illustrative purposes only. # Use self.fields.FormXYZ.etcetc instead.

comb += field(msr, MSRb.TEs, MSRb.TEe).eq(0)

Proof by substitution:

field(insn, 0, 6, field_width=32).eq(17)

== insn[field_slice(0, 6, field_width=32)].eq(17) == insn[slice((31-6), (31-0)+1)].eq(17) == insn[slice(25, 32)].eq(17) == insn[25:32].eq(17)

field(msr, MSRb.TEs, MSRb.TEe).eq(0)

== field(msr, 53, 54).eq(0) == msr[field_slice(53, 54)].eq(0) == msr[slice((63-54), (63-53)+1)].eq(0) # note cross-over! == msr[slice(9, 11)].eq(0) == msr[9:11].eq(0)

openpower.consts.field_slice(msb0_start, msb0_end, field_width=64)

Answers with a subfield slice of the signal r (“register”), where the start and end bits use IBM “MSB 0” conventions.

see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering

  • assertion: msb0_start < msb0_end.
  • The range specified is inclusive on both ends.
  • field_width specifies the total number of bits (note: not bits-1)

openpower.endian module

openpower.endian.set_endian_mode(mode)

openpower.exceptions module

exceptions

class openpower.exceptions.LDSTException(name=None)

Bases: nmutil.iocontrol.RecordObject

openpower.state module

class openpower.state.CoreState(name)

Bases: nmutil.iocontrol.RecordObject

contains “Core State Information” which says exactly where things are

example: eint says to PowerDecoder that it should fire an exception rather than let the current decoded instruction proceed. likewise if dec goes negative. MSR contains LE/BE and Priv state. PC contains the Program Counter, and SVSTATE is the Sub-Program-Counter.

openpower.util module

openpower.util.fast_reg_to_spr(spr_num)
openpower.util.log_rand(n, min_val=1)
openpower.util.mask_extend(x, nbits, repeat)
openpower.util.slow_reg_to_spr(slow_reg)
openpower.util.spr_to_fast_reg(spr_num)
openpower.util.spr_to_slow_reg(spr_num)

Module contents