openpower.test.alu package

Submodules

openpower.test.alu.alu_cases module

class openpower.test.alu.alu_cases.ALUTestCase

Bases: openpower.test.common.TestAccumulatorBase

case_0_adde()
case_1_regression()
case_addis_nonzero_r0()
case_addis_nonzero_r0_regression()
case_addme_ca_0()
case_addme_ca_1()
case_addme_ca_so_3()

bug where SO does not get passed through to CR0

case_addze()
case_cmp()
case_cmp2()
case_cmp3()
case_cmpeqb()
case_cmpl_microwatt_0()

microwatt 1.bin: 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10

register_file.vhdl: Reading GPR 11 000000000001C026 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025 cr_file.vhdl: Reading CR 35055050 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
case_cmpl_microwatt_0_disasm()

microwatt 1.bin: disassembled version 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10

register_file.vhdl: Reading GPR 11 000000000001C026 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025 cr_file.vhdl: Reading CR 35055050 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
case_cmpli_microwatt()

microwatt 1.bin: cmpli 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132

gpr: 00000000301fc7a7 <- r13 cr : 0000000090215393 xer: so 1 ca 0 32 0 ov 0 32 0
case_cmplw_microwatt_1()

microwatt 1.bin: 10d94: 40 20 96 7c cmplw cr1,r22,r4

gpr: 00000000ffff6dc1 <- r4 gpr: 0000000000000000 <- r22
case_extsb()
case_rand()
case_rand_imm()

openpower.test.alu.svp64_cases module

class openpower.test.alu.svp64_cases.SVP64ALUTestCase

Bases: openpower.test.common.TestAccumulatorBase

case_13_sv_predicated_add()
>>> lst = [
    'sv.add/m=r30 1.v, 5.v, 9.v',
    'sv.add/m=~r30 13.v, 10.v, 7.v'
]

checks integer predication using mask-invertmask. real-world usage would be two different operations (a masked-add and an inverted-masked-sub, where the mask was set up as part of a parallel If-Then-Else)

first add:
  • 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
  • 2 = 0 (skipped)
  • 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230
second add:
  • 13 = 0 (skipped)
  • 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051
  • 15 = 0 (skipped)
case_14_intpred_all_zeros_all_ones()
>>> lst = [
    'sv.add/m=r30 1.v, 5.v, 9.v',
    'sv.add/m=~r30 13.v, 10.v, 7.v'
]

checks an instruction with no effect (all mask bits are zeros). TODO: check completion time (number of cycles), although honestly it is an implementation-specific optimisation to decide to skip Vector operations with a fully-zero mask.

first add:
  • 1 = 0 (skipped)
  • 2 = 0 (skipped)
  • 3 = 0 (skipped)
second add:
  • 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230
  • 14 = 11 + 8 => 0xB063 = 0x3012 + 0x8051
  • 15 = 12 + 9 => 0x7736 = 0x6502 + 0x1234
case_18_sv_add_cr_pred()
>>> lst = ['sv.add/m=ne 1.v, 5.v, 9.v']
adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
  • 1 = 5 + 9 => not to be touched (skipped)
  • 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
expected results:
  • r1 = 0xbeef skipped since CR4 is 1 and test is inverted
  • r2 = 0x3334 CR5 is 0, so this is used
case_1_sv_add()
>>> lst = ['sv.add 1.v, 5.v, 9.v']
adds:
  • 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
  • 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
case_2_sv_add_scalar()
>>> lst = ['sv.add 1, 5, 9']
adds:
  • 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
case_3_sv_check_extra()
>>> lst = ['sv.add 13.v, 10.v, 7.v']
adds:
  • 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012

This case helps checking the encoding of the Extra field It was built so the v3.0b registers are: 3, 2, 1 and the Extra field is: 101.110.111 The expected SVP64 register numbers are: 13, 10, 7 Any mistake in decoding will probably give a different answer

case_4_sv_add_()
>>> lst = ['sv.add. 1.v, 5.v, 9.v']
adds when Rc=1: TODO CRs higher up
  • 1 = 5 + 9 => 0 = -1+1 CR0=0b100
  • 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
case_5_sv_check_vl_0()
>>> lst = [
    'sv.add 13.v, 10.v, 7.v',  # skipped, because VL == 0
    'add 1, 5, 9'
]
adds:
  • 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
case_6_sv_add_multiple()
>>> lst = [
    'sv.add 1.v, 5.v, 9.v',
    'sv.add 13.v, 10.v, 7.v'
]
adds:
  • 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
  • 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
  • 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230
  • 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230
  • 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000
  • 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234
case_7_sv_add_2()
>>> lst = ['sv.add 1, 5.v, 9.v']
adds:
  • 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
case_8_sv_add_3()
>>> lst = ['sv.add 1.v, 5, 9.v']
adds:
  • 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
  • 2 = 5 + 10 => 0x5432 = 0x4321+0x1111

Module contents