openpower.decoder package

Subpackages

Submodules

openpower.decoder.decode2execute1 module

Decode2ToExecute1Type

based on Anton Blanchard microwatt decode2.vhdl

class openpower.decoder.decode2execute1.Data(width, name)

Bases: nmigen.hdl.rec.Record

ports()
class openpower.decoder.decode2execute1.Decode2ToExecute1Type(name=None, asmcode=True, opkls=None, do=None, regreduce_en=False)

Bases: nmutil.iocontrol.RecordObject

class openpower.decoder.decode2execute1.Decode2ToOperand(name=None)

Bases: openpower.decoder.decode2execute1.IssuerDecode2ToOperand

class openpower.decoder.decode2execute1.IssuerDecode2ToOperand(name=None)

Bases: nmutil.iocontrol.RecordObject

contains the subset of fields needed for Issuer to decode the instruction and get register rdflags signals set up. it also doubles up as the “Trap” temporary store, because part of the Decoder’s job is to identify whether a trap / interrupt / exception should occur.

openpower.decoder.helpers module

openpower.decoder.helpers.EXTS(value)

extends sign bit out from current MSB to all 256 bits

openpower.decoder.helpers.EXTS128(value)

extends sign bit out from current MSB to 128 bits

openpower.decoder.helpers.EXTS64(value)

extends sign bit out from current MSB to 64 bits

openpower.decoder.helpers.EXTZ64(value)
class openpower.decoder.helpers.HelperTests(methodName='runTest')

Bases: unittest.case.TestCase

assertHex(a, b)
test_EXTS64()
test_MASK()
test_ROTL32()
test_ROTL64()
openpower.decoder.helpers.MASK(x, y)
openpower.decoder.helpers.MASK32(x, y)
openpower.decoder.helpers.MODS(n, d)

Links: * https://bugs.libre-soc.org/show_bug.cgi?id=324 - add trunc_div and trunc_rem

openpower.decoder.helpers.MULS(a, b)
openpower.decoder.helpers.ROTL32(value, bits)
openpower.decoder.helpers.ROTL64(value, bits)
openpower.decoder.helpers.eq(a, b)
openpower.decoder.helpers.exts(value, bits)
openpower.decoder.helpers.ge(a, b)
openpower.decoder.helpers.gt(a, b)
openpower.decoder.helpers.le(a, b)
openpower.decoder.helpers.length(a)
openpower.decoder.helpers.lt(a, b)
openpower.decoder.helpers.ne(a, b)
openpower.decoder.helpers.rotl(value, bits, wordlen)
openpower.decoder.helpers.undefined(v)

function that, for Power spec purposes, returns undefined bits of the same shape as the input bits. however, for purposes of matching POWER9’s behavior returns the input bits unchanged. this effectively “marks” (tags) locations in the v3.0B spec that need to be submitted for clarification.

openpower.decoder.orderedset module

class openpower.decoder.orderedset.OrderedSet(iterable=None)

Bases: collections.abc.MutableSet

add(key)

Add an element.

discard(key)

Remove an element. Do not raise an exception if absent.

openpower.decoder.power_decoder module

Cascading Power ISA Decoder

License: LGPLv3+

# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net> # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>

This module uses CSV tables in a hierarchical/peer cascading fashion, to create a multi-level instruction decoder by recognising appropriate patterns. The output is a wide, flattened (1-level) series of bitfields, suitable for a simple RISC engine.

This is based on Anton Blanchard’s excellent microwatt work: https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl

The basic principle is that the python code does the heavy lifting (reading the CSV files, constructing the hierarchy), creating the HDL AST with for-loops generating switch-case statements.

Where “normal” HDL would do this, in laborious excruciating detail:

switch (opcode & major_mask_bits):

case opcode_2: decode_opcode_2() case opcode_19:

switch (opcode & minor_19_mask_bits)
case minor_opcode_19_operation_X: case minor_opcode_19_operation_y:

we take full advantage of the decoupling between python and the nmigen AST data structure, to do this:

with m.Switch(opcode & self.mask):
for case_bitmask in subcases:
with m.If(opcode & case_bitmask): {do_something}

this includes specifying the information sufficient to perform subdecoding.

create_pdecode()

the full hierarchical tree for decoding POWER9 is specified here subsetting is possible by specifying col_subset (row_subset TODO)

PowerDecoder

takes a list of CSV files with an associated bit-range that it is requested to match against the “opcode” row of the CSV file. This pattern can be either an integer, a binary number, or a wildcard nmigen Case pattern of the form “001–1-100”.

Subdecoders

these are additional cases with further decoding. The “pattern” argument is specified as one of the Case statements (a peer of the opcode row in the CSV file), and thus further fields of the opcode may be decoded giving increasing levels of detail.

Top Level:

[ (extra.csv: bit-fields entire 32-bit range
opcode -> matches 000000—————01000000000 -> ILLEGAL instruction 01100000000000000000000000000000 -> SIM_CONFIG instruction ………………………….. ->

), (major.csv: first 6 bits ONLY

opcode -> matches 001100 -> ALU,OP_ADD (add) 001101 -> ALU,OP_ADD (another type of add) …… -> … …… -> … subdecoders: 001011 this must match MAJOR.CSV

[ (minor_19.csv: bits 21 through 30 inclusive:
opcode -> matches 0b0000000000 -> ALU,OP_MCRF ………… -> ….

), (minor_19_00000.csv: bits 21 through 25 inclusive:

opcode -> matches 0b00010 -> ALU,add_pcis

)

]

),

]

class openpower.decoder.power_decoder.PowerDecoder(width, dec, name=None, col_subset=None, row_subset=None)

Bases: nmigen.hdl.ir.Elaboratable

PowerDecoder - decodes an incoming opcode into the type of operation

this is a recursive algorithm, creating Switch statements that can have further match-and-decode on other parts of the opcode field before finally landing at a “this CSV entry details gets returned” thing.

the complicating factor is the row and col subsetting. column subsetting dynamically chooses only the CSV columns requested, whilst row subsetting allows a function to be called on the row to determine if the Case statement is to be generated for that row. this not only generates completely different Decoders, it also means that some sub-decoders will turn up blank (empty switch statements). if that happens we do not want the parent to include a Mux for an entirely blank switch statement so we have to store the switch/case statements in a tree, and post-analyse it.

the reason for the tree is because elaborate can only be called after the constructor is called. all quite messy.

divide_opcodes(d)
elaborate(platform)
handle_subdecoders(switch_case, submodules, d)
ports()
suffix_mask(d)
tree_analyse()
class openpower.decoder.power_decoder.PowerOp(incl_asm=True, name=None, subset=None)

Bases: object

PowerOp - a dynamic class that stores (subsets of) CSV rows of data about a PowerISA instruction. this is a “micro-code” expanded format which generates an awful lot of wires, hence the subsetting

eq(otherop)
ports()
class openpower.decoder.power_decoder.Subdecoder(pattern, opcodes, opint, bitsel, suffix, subdecoders)

Bases: tuple

bitsel

Alias for field number 3

opcodes

Alias for field number 1

opint

Alias for field number 2

pattern

Alias for field number 0

subdecoders

Alias for field number 5

suffix

Alias for field number 4

class openpower.decoder.power_decoder.TopPowerDecoder(width, dec, name=None, col_subset=None, row_subset=None)

Bases: openpower.decoder.power_decoder.PowerDecoder

top-level hierarchical decoder for POWER ISA bigendian dynamically switches between big and little endian decoding (reverses byte order). See V3.0B p44 1.11.2

elaborate(platform)
form_names
ports()
openpower.decoder.power_decoder.create_pdecode(name=None, col_subset=None, row_subset=None)

create_pdecode - creates a cascading hierarchical POWER ISA decoder

subsetting of the PowerOp decoding is possible by setting col_subset

openpower.decoder.power_decoder.get_pname(field, pname)

openpower.decoder.power_decoder2 module

Power ISA Decoder second stage

based on Anton Blanchard microwatt decode2.vhdl

Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by over-riding the internal opcode when an exception is needed.

class openpower.decoder.power_decoder2.DecodeA(dec, regreduce_en)

Bases: nmigen.hdl.ir.Elaboratable

DecodeA from instruction

decodes register RA, implicit and explicit CSRs

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeAImm(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeA immediate from instruction

decodes register RA, whether immediate-zero, implicit and explicit CSRs. SVP64 mode requires 2 extra bits

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeB(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeB from instruction

decodes register RB, different forms of immediate (signed, unsigned), and implicit SPRs. register B is basically “lane 2” into the CompUnits. by industry-standard convention, “lane 2” is where fully-decoded immediates are muxed in.

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeBImm(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeB immediate from instruction

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeC(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeC from instruction

decodes register RC. this is “lane 3” into some CompUnits (not many)

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeCRIn(dec)

Bases: nmigen.hdl.ir.Elaboratable

Decodes input CR from instruction

CR indices - insn fields - (not the data in the CR) require only 3 bits because they refer to CR0-CR7

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeCROut(dec)

Bases: nmigen.hdl.ir.Elaboratable

Decodes input CR from instruction

CR indices - insn fields - (not the data in the CR) require only 3 bits because they refer to CR0-CR7

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeOE(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeOE from instruction

decodes OE field: uses RC decode detection which might not be good

– For now, use “rc” in the decode table to decide whether oe exists. – This is not entirely correct architecturally: For mulhd and – mulhdu, the OE field is reserved. It remains to be seen what an – actual POWER9 does if we set it on those instructions, for now we – test that further down when assigning to the multiplier oe input.

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeOut(dec, regreduce_en)

Bases: nmigen.hdl.ir.Elaboratable

DecodeOut from instruction

decodes output register RA, RT or SPR

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeOut2(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeOut2 from instruction

decodes output registers (2nd one). note that RA is implicit below, which now causes problems with SVP64

TODO: SVP64 is a little more complex, here. svp64 allows extending by one more destination by having one more EXTRA field. RA-as-src is not the same as RA-as-dest. limited in that it’s the same first 5 bits (from the v3.0B opcode), but still kinda cool. mostly used for operations that have src-as-dest: mostly this is LD/ST-with-update but there are others.

elaborate(platform)
class openpower.decoder.power_decoder2.DecodeRC(dec)

Bases: nmigen.hdl.ir.Elaboratable

DecodeRc from instruction

decodes Record bit Rc

elaborate(platform)
class openpower.decoder.power_decoder2.PowerDecode2(dec, opkls=None, fn_name=None, final=False, state=None, svp64_en=True, regreduce_en=False)

Bases: openpower.decoder.power_decoder2.PowerDecodeSubset

PowerDecode2: the main instruction decoder.

whilst PowerDecode is responsible for decoding the actual opcode, this module encapsulates further specialist, sparse information and expansion of fields that is inconvenient to have in the CSV files. for example: the encoding of the immediates, which are detected and expanded out to their full value from an annotated (enum) representation.

implicit register usage is also set up, here. for example: OP_BC requires implicitly reading CTR, OP_RFID requires implicitly writing to SRR1 and so on.

in addition, PowerDecoder2 is responsible for detecting whether instructions are illegal (or privileged) or not, and instead of just leaving at that, replacing the instruction to execute with a suitable alternative (trap).

LDSTExceptions are done the cycle _after_ they’re detected (after they come out of LDSTCompUnit). basically despite the instruction being decoded, the results of the decode are completely ignored and “exception.happened” used to set the “actual” instruction to “OP_TRAP”. the LDSTException data structure gets filled in, in the CompTrapOpSubset and that’s what it fills in SRR.

to make this work, TestIssuer must notice “exception.happened” after the (failed) LD/ST and copies the LDSTException info from the output, into here (PowerDecoder2). without incrementing PC.

elaborate(platform)
get_col_subset(opkls)
trap(m, traptype, trapaddr, ldst_exc=None)

trap: this basically “rewrites” the decoded instruction as a trap

class openpower.decoder.power_decoder2.PowerDecodeSubset(dec, opkls=None, fn_name=None, final=False, state=None, svp64_en=True, regreduce_en=False)

Bases: nmigen.hdl.ir.Elaboratable

PowerDecodeSubset: dynamic subset decoder

only fields actually requested are copied over. hence, “subset” (duh).

do_copy(field, val, final=False)
do_get(field, final=False)
elaborate(platform)
get_col_subset(do)
needs_field(field, op_field)
op_get(op_field)
ports()
rowsubsetfn(opcode, row)

select per-Function-Unit subset of opcodes to be processed

normally this just looks at the “unit” column. MMU is different in that it processes specific SPR set/get operations that the SPR pipeline should not.

class openpower.decoder.power_decoder2.SPRMap(regreduce_en)

Bases: nmigen.hdl.ir.Elaboratable

SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow

elaborate(platform)
openpower.decoder.power_decoder2.decode_spr_num(spr)
openpower.decoder.power_decoder2.get_rdflags(e, cu)
openpower.decoder.power_decoder2.instr_is_priv(m, op, insn)

determines if the instruction is privileged or not

openpower.decoder.power_enums module

Enums used in OpenPOWER ISA decoding

Note: for SV, from v3.1B p12:

The designated SPR sandbox consists of non-privileged SPRs 704-719 and privileged SPRs 720-735.

Note: the option exists to select a much shorter list of SPRs, to reduce regfile size in HDL. this is SPRreduced and the supported list is in get_spr_enum

class openpower.decoder.power_enums.CRInSel

Bases: enum.Enum

An enumeration.

BA_BB = 4
BC = 5
BFA = 3
BI = 2
CR0 = 1
CR1 = 7
NONE = 0
WHOLE_REG = 6
class openpower.decoder.power_enums.CROutSel

Bases: enum.Enum

An enumeration.

BF = 2
BT = 3
CR0 = 1
CR1 = 5
NONE = 0
WHOLE_REG = 4
class openpower.decoder.power_enums.CryIn

Bases: enum.Enum

An enumeration.

CA = 2
ONE = 1
ZERO = 0
class openpower.decoder.power_enums.Form

Bases: enum.Enum

An enumeration.

A = 18
B = 2
D = 4
DQ = 6
DS = 5
DX = 7
EVS = 26
EVX = 25
I = 1
M = 19
MD = 20
MDS = 21
NONE = 0
SC = 3
SVL = 29
VA = 22
VC = 23
VX = 24
X = 8
XFL = 11
XFX = 10
XL = 9
XO = 17
XS = 16
XX1 = 12
XX2 = 13
XX3 = 14
XX4 = 15
Z22 = 27
Z23 = 28
class openpower.decoder.power_enums.Function

Bases: enum.Enum

An enumeration.

ALU = 2
BRANCH = 32
CR = 64
DIV = 512
LDST = 4
LOGICAL = 16
MMU = 2048
MUL = 256
NONE = 0
SHIFT_ROT = 8
SPR = 1024
SV = 4096
TRAP = 128
VL = 8192
class openpower.decoder.power_enums.In1Sel

Bases: enum.Enum

An enumeration.

NONE = 0
RA = 1
RA_OR_ZERO = 2
RS = 4
SPR = 3
class openpower.decoder.power_enums.In2Sel

Bases: enum.Enum

An enumeration.

CONST_BD = 7
CONST_DS = 8
CONST_LI = 6
CONST_M1 = 9
CONST_SH = 10
CONST_SH32 = 11
CONST_SI = 3
CONST_SI_HI = 5
CONST_UI = 2
CONST_UI_HI = 4
NONE = 0
RB = 1
RS = 13
SPR = 12
class openpower.decoder.power_enums.In3Sel

Bases: enum.Enum

An enumeration.

NONE = 0
RB = 2
RS = 1
class openpower.decoder.power_enums.LDSTMode

Bases: enum.Enum

An enumeration.

NONE = 0
cix = 2
cx = 3
update = 1
class openpower.decoder.power_enums.LdstLen

Bases: enum.Enum

An enumeration.

NONE = 0
is1B = 1
is2B = 2
is4B = 4
is8B = 8
class openpower.decoder.power_enums.MicrOp

Bases: enum.Enum

An enumeration.

OP_ADD = 2
OP_ADDPCIS = 3
OP_AND = 4
OP_ATTN = 5
OP_B = 6
OP_BC = 7
OP_BCREG = 8
OP_BPERM = 9
OP_CMP = 10
OP_CMPB = 11
OP_CMPEQB = 12
OP_CMPRB = 13
OP_CNTZ = 14
OP_CRAND = 15
OP_CRANDC = 16
OP_CREQV = 17
OP_CRNAND = 18
OP_CRNOR = 19
OP_CROP = 69
OP_CROR = 20
OP_CRORC = 21
OP_CRXOR = 22
OP_DARN = 23
OP_DCBF = 24
OP_DCBST = 25
OP_DCBT = 26
OP_DCBTST = 27
OP_DCBZ = 28
OP_DIV = 29
OP_DIVE = 30
OP_EXTS = 31
OP_EXTSWSLI = 32
OP_ICBI = 33
OP_ICBT = 34
OP_ILLEGAL = 0
OP_ISEL = 35
OP_ISYNC = 36
OP_LOAD = 37
OP_MADDHD = 39
OP_MADDHDU = 40
OP_MADDLD = 41
OP_MCRF = 42
OP_MCRXR = 43
OP_MCRXRX = 44
OP_MFCR = 45
OP_MFMSR = 71
OP_MFSPR = 46
OP_MOD = 47
OP_MTCRF = 48
OP_MTMSR = 74
OP_MTMSRD = 72
OP_MTSPR = 49
OP_MUL_H32 = 52
OP_MUL_H64 = 51
OP_MUL_L64 = 50
OP_NOP = 1
OP_OR = 53
OP_POPCNT = 54
OP_PRTY = 55
OP_RFID = 70
OP_RLC = 56
OP_RLCL = 57
OP_RLCR = 58
OP_SC = 73
OP_SETB = 59
OP_SETVL = 76
OP_SHL = 60
OP_SHR = 61
OP_SIM_CONFIG = 68
OP_STORE = 38
OP_SYNC = 62
OP_TLBIE = 75
OP_TRAP = 63
OP_XOR = 67
class openpower.decoder.power_enums.OutSel

Bases: enum.Enum

An enumeration.

NONE = 0
RA = 2
RT = 1
RT_OR_ZERO = 4
SPR = 3
class openpower.decoder.power_enums.RC

Bases: enum.Enum

An enumeration.

NONE = 0
ONE = 1
RC = 2
openpower.decoder.power_enums.SPRfull

alias of openpower.decoder.power_enums.SPR

openpower.decoder.power_enums.SPRreduced

alias of openpower.decoder.power_enums.SPR

class openpower.decoder.power_enums.SVEXTRA

Bases: enum.Enum

An enumeration.

Idx0 = 1
Idx1 = 2
Idx2 = 3
Idx3 = 4
Idx_1_2 = 5
NONE = 0
class openpower.decoder.power_enums.SVEtype

Bases: enum.Enum

An enumeration.

EXTRA2 = 1
EXTRA3 = 2
NONE = 0
class openpower.decoder.power_enums.SVP64PredCR

Bases: enum.Enum

An enumeration.

EQ = 4
GE = 1
GT = 2
LE = 3
LT = 0
NE = 5
NS = 7
SO = 6
class openpower.decoder.power_enums.SVP64PredInt

Bases: enum.Enum

An enumeration.

ALWAYS = 0
R10 = 4
R10_N = 5
R3 = 2
R30 = 6
R30_N = 7
R3_N = 3
R3_UNARY = 1
class openpower.decoder.power_enums.SVP64PredMode

Bases: enum.Enum

An enumeration.

ALWAYS = 0
CR = 2
INT = 1
class openpower.decoder.power_enums.SVP64RMMode

Bases: enum.Enum

An enumeration.

FFIRST = 2
MAPREDUCE = 1
NORMAL = 0
PREDRES = 4
SATURATE = 3
class openpower.decoder.power_enums.SVP64sat

Bases: enum.Enum

An enumeration.

NONE = 0
SIGNED = 1
UNSIGNED = 2
class openpower.decoder.power_enums.SVP64subvl

Bases: enum.Enum

An enumeration.

VEC1 = 0
VEC2 = 1
VEC3 = 2
VEC4 = 3
class openpower.decoder.power_enums.SVP64width

Bases: enum.Enum

An enumeration.

DEFAULT = 0
EW_16 = 2
EW_32 = 1
EW_8 = 3
class openpower.decoder.power_enums.SVPtype

Bases: enum.Enum

An enumeration.

NONE = 0
P1 = 1
P2 = 2
openpower.decoder.power_enums.find_wiki_dir()
openpower.decoder.power_enums.find_wiki_file(name)
openpower.decoder.power_enums.get_csv(name)
openpower.decoder.power_enums.get_signal_name(name)
openpower.decoder.power_enums.get_spr_enum(full_file)

get_spr_enum - creates an Enum of SPRs, dynamically has the option to reduce the enum to a much shorter list. this saves drastically on the size of the regfile

openpower.decoder.power_fields module

class openpower.decoder.power_fields.BitRange

Bases: collections.OrderedDict

BitRange: remaps from straight indices (0,1,2..) to bit numbers

class openpower.decoder.power_fields.DecodeFields(bitkls=<class 'openpower.decoder.power_fields.BitRange'>, bitargs=(), fname=None, name_on_wiki=None)

Bases: object

create_specs()
decode_fields()
decode_instruction_fields(fields)
form_names
openpower.decoder.power_fields.decode_form(form)
openpower.decoder.power_fields.decode_form_header(hdr)
openpower.decoder.power_fields.decode_instructions(form)
openpower.decoder.power_fields.decode_line(header, line)
openpower.decoder.power_fields.find_unique(d, key)

openpower.decoder.power_fieldsn module

class openpower.decoder.power_fieldsn.SigDecode(width)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
ports()
class openpower.decoder.power_fieldsn.SignalBitRange(signal)

Bases: openpower.decoder.power_fields.BitRange

openpower.decoder.power_fieldsn.create_sigdecode()

openpower.decoder.power_pseudo module

openpower.decoder.power_pseudo.convert_to_python(pcode, form, incl_carry)
openpower.decoder.power_pseudo.get_reg_hex(reg)
openpower.decoder.power_pseudo.test()
openpower.decoder.power_pseudo.tolist(num)

openpower.decoder.power_regspec_map module

regspec_decode

functions for the relationship between regspecs and Decode2Execute1Type

these functions encodes the understanding (relationship) between Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2).

based on the regspec, which contains the register file name and register name, return a tuple of:

  • how the decoder should determine whether the Function Unit needs access to a given Regport or not
  • which Regfile number on that port should be read to get that data
  • when it comes to writing: likewise, which Regfile num should be written

Note that some of the port numbering encoding is unary. in the case of “Full Condition Register”, it’s a full 8-bit mask of read/write-enables. This actually matches directly with the XFX field in MTCR, and at some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO).

For the INT and CR numbering, these are expressed in binary in the instruction and need to be converted to unary (1<<read_reg1.data). Note however that XFX in MTCR is unary-masked!

XER regs are implicitly-encoded (hard-coded) based on whether the operation has carry or overflow.

FAST regfile is, again, implicitly encoded, back in PowerDecode2, based on the type of operation (see DecodeB for an example, where fast_out is set, then carried into read_fast2 in PowerDecode2).

The SPR regfile on the other hand is binary-encoded, and, furthermore, has to be “remapped” to internal SPR Enum indices (see SPRMap in PowerDecode2) see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs

openpower.decoder.power_regspec_map.regspec_decode_read(e, regfile, name)
openpower.decoder.power_regspec_map.regspec_decode_write(e, regfile, name)

openpower.decoder.power_svp64 module

class openpower.decoder.power_svp64.SVP64RM(microwatt_format=False)

Bases: object

get_svp64_csv(fname)
openpower.decoder.power_svp64.decode_extra(rm, prefix='')
openpower.decoder.power_svp64.get_regtype(regname)
openpower.decoder.power_svp64.is_CR_3bit(regname)
openpower.decoder.power_svp64.is_CR_5bit(regname)
openpower.decoder.power_svp64.is_GPR(regname)

openpower.decoder.power_svp64_extra module

SVP64 EXTRA field decoder

class openpower.decoder.power_svp64_extra.SVP64CRExtra

Bases: openpower.decoder.power_svp64_extra.SVP64ExtraSpec

SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension

incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector depending on info in one of the positions in the EXTRA field.

yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.

designed so that “no change” to the 3-bit CR register number occurs if SV either does not apply or the relevant EXTRA2/3 field bits are zero.

see https://libre-soc.org/openpower/sv/svp64/appendix

elaborate(platform)
class openpower.decoder.power_svp64_extra.SVP64ExtraSpec

Bases: nmigen.hdl.ir.Elaboratable

SVP64ExtraSpec - decodes SVP64 Extra specification.

selects the required EXTRA2/3 field.

see https://libre-soc.org/openpower/sv/svp64/

elaborate(platform)
class openpower.decoder.power_svp64_extra.SVP64RegExtra

Bases: openpower.decoder.power_svp64_extra.SVP64ExtraSpec

SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension

incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector depending on info in one of the positions in the EXTRA field.

designed so that “no change” to the 5-bit register number occurs if SV either does not apply or the relevant EXTRA2/3 field bits are zero.

see https://libre-soc.org/openpower/sv/svp64/

elaborate(platform)

openpower.decoder.power_svp64_prefix module

SVP64 Prefix Decoder

class openpower.decoder.power_svp64_prefix.SVP64PrefixDecoder

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
ports()

openpower.decoder.power_svp64_rm module

SVP64 RM (Remap) Record.

https://libre-soc.org/openpower/sv/svp64/

Field Name | Field bits | Description |

|-------------|————|----------------------------------------| | MASKMODE | 0 | Execution (predication) Mask Kind | | MASK | 1:3 | Execution Mask | | ELWIDTH | 4:5 | Element Width | | ELWIDTH_SRC | 6:7 | Element Width for Source | | SUBVL | 8:9 | Sub-vector length | | EXTRA | 10:18 | context-dependent extra | | MODE | 19:23 | changes Vector behaviour |

class openpower.decoder.power_svp64_rm.SVP64RMModeDecode(name=None)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
openpower.decoder.power_svp64_rm.sv_input_record_layout = [('sv_pred_sz', 1), ('sv_pred_dz', 1), ('sv_saturate', <enum 'SVP64sat'>), ('SV_Ptype', <enum 'SVPtype'>)]

RM Mode there are three Mode variants, two for LD/ST and one for everything else https://libre-soc.org/openpower/sv/svp64/ https://libre-soc.org/openpower/sv/ldst/

LD/ST immed: 00 str sz dz normal mode 01 inv CR-bit Rc=1: ffirst CR sel 01 inv els RC1 Rc=0: ffirst z/nonz 10 N dz els sat mode: N=0/1 u/s 11 inv CR-bit Rc=1: pred-result CR sel 11 inv els RC1 Rc=0: pred-result z/nonz

LD/ST indexed: 00 0 sz dz normal mode 00 1 rsvd reserved 01 inv CR-bit Rc=1: ffirst CR sel 01 inv dz RC1 Rc=0: ffirst z/nonz 10 N sz dz sat mode: N=0/1 u/s 11 inv CR-bit Rc=1: pred-result CR sel 11 inv dz RC1 Rc=0: pred-result z/nonz

Arithmetic: 00 0 sz dz normal mode 00 1 dz CRM reduce mode (mapreduce), SUBVL=1 00 1 SVM CRM subvector reduce mode, SUBVL>1 01 inv CR-bit Rc=1: ffirst CR sel 01 inv dz RC1 Rc=0: ffirst z/nonz 10 N sz dz sat mode: N=0/1 u/s 11 inv CR-bit Rc=1: pred-result CR sel 11 inv dz RC1 Rc=0: pred-result z/nonz

openpower.decoder.selectable_int module

class openpower.decoder.selectable_int.FieldSelectableInt(si, br)

Bases: object

FieldSelectableInt: allows bit-range selection onto another target

asint(msb0=False)
eq(b)
get_range()
merge(vi)
class openpower.decoder.selectable_int.FieldSelectableIntTestCase(methodName='runTest')

Bases: unittest.case.TestCase

test_arith()
test_select()
test_select_range()
class openpower.decoder.selectable_int.SelectableInt(value, bits)

Bases: object

SelectableInt - a class that behaves exactly like python int

this class is designed to mirror precisely the behaviour of python int. the only difference is that it must contain the context of the bitwidth (number of bits) associated with that integer.

FieldSelectableInt can then operate on partial bits, and because there is a bit width associated with SelectableInt, slices operate correctly including negative start/end points.

asint()
eq(b)
narrow(bits)
to_signed_int()
class openpower.decoder.selectable_int.SelectableIntTestCase(methodName='runTest')

Bases: unittest.case.TestCase

test_arith()
test_cmp()
test_concat()
test_get()
test_logic()
test_repr()
test_set()
test_unsigned()
openpower.decoder.selectable_int.check_extsign(a, b)
openpower.decoder.selectable_int.onebit(bit)
openpower.decoder.selectable_int.selectassign(lhs, idx, rhs)
openpower.decoder.selectable_int.selectconcat(*args, repeat=1)
openpower.decoder.selectable_int.selectgtu(lhs, rhs)

greater-than (unsigned)

openpower.decoder.selectable_int.selectltu(lhs, rhs)

less-than (unsigned)

Module contents