openpower.simulator package

Submodules

openpower.simulator.envcmds module

openpower.simulator.gas module

openpower.simulator.gas.get_assembled_instruction(instruction, bigendian=False)

openpower.simulator.program module

POWER Program

takes powerpc assembly instructions and turns them into LE/BE binary data. calls powerpc64-linux-gnu-as, ld and objcopy to do so.

class openpower.simulator.program.Program(instructions, bigendian)

Bases: object

close()
generate_instructions()
reset()
size()
write_bin(fname)

openpower.simulator.qemu module

class openpower.simulator.qemu.QemuController(kernel, bigendian)

Bases: object

break_address(addr)
connect()
delete_breakpoint(breakpoint=None)
exit()
gdb_continue()
gdb_eval(expr)
get_cr()
get_ctr()
get_fpscr()
get_lr()
get_mem(addr, nbytes)
get_mq()
get_msr()
get_pc()
get_register(num)
get_registers()
get_xer()
set_byte(addr, v)
set_endian(bigendian)
step()
openpower.simulator.qemu.run_program(program, initial_mem=None, extra_break_addr=None, bigendian=False)
openpower.simulator.qemu.swap_order(x, nbytes)

openpower.simulator.test_div_sim module

class openpower.simulator.test_div_sim.DivDecoderTestCase(name='div')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_div_sim.DivTestCases

class openpower.simulator.test_div_sim.DivTestCases(name='div')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_0_divw()
test_1_divw_()
test_1_divwe()
test_2_divw_()
test_2_divweu()
test_4_moduw()
test_5_div_regression()
test_data = []
class openpower.simulator.test_div_sim.DivZeroDecoderTestCase(name='divbyzero')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_div_sim.DivZeroTestCases

class openpower.simulator.test_div_sim.DivZeroTestCases(name='divbyzero')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_0_divw()
test_1_divwe()
test_2_divweu()
test_4_moduw()
test_data = []

openpower.simulator.test_helloworld_sim module

class openpower.simulator.test_helloworld_sim.HelloDecoderTestCase(name='div')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_helloworld_sim.HelloTestCases

class openpower.simulator.test_helloworld_sim.HelloTestCases(name='div')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None, extra_break_addr=None)
test_data = []
test_microwatt_helloworld()

openpower.simulator.test_mul_sim module

class openpower.simulator.test_mul_sim.MulDecoderTestCase(name='div')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_mul_sim.MulTestCases

class openpower.simulator.test_mul_sim.MulTestCases(name='div')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_data = []
test_mullwo()
tst_mullw()

openpower.simulator.test_shift_sim module

class openpower.simulator.test_shift_sim.MulDecoderTestCase(name='div')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_shift_sim.MulTestCases

class openpower.simulator.test_shift_sim.MulTestCases(name='div')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_1_extswsli()
test_data = []

openpower.simulator.test_sim module

class openpower.simulator.test_sim.AttnTestCase(name='general')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_0_attn()

simple test of attn. program is 4 long: should halt at 2nd op

test_data = []
class openpower.simulator.test_sim.DecoderBase

Bases: object

qemu_mem_compare(sim, qemu, check=True)
qemu_register_compare(sim, qemu, regs)
run_tst(generator, initial_mem=None, initial_pc=0)
run_tst_program(prog, reglist, initial_mem=None, extra_break_addr=None)
class openpower.simulator.test_sim.DecoderTestCase(name='general')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_sim.GeneralTestCases

class openpower.simulator.test_sim.GeneralTestCases(name='general')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_0_cmp()
test_0_ldst_widths()
test_0_litex_bios_cmp()

litex bios cmp test

test_0_litex_bios_ctr_loop()

32a4: ff ff 63 38 addi r3,r3,-1 32a8: 20 00 63 78 clrldi r3,r3,32 32ac: 01 00 23 39 addi r9,r3,1 32b0: a6 03 29 7d mtctr r9 32b4: 00 00 00 60 nop 32b8: fc ff 00 42 bdnz 32b4 <cdelay+0x10> 32bc: 20 00 80 4e blr

notes on converting pseudo-assembler to actual:

  • bdnz target (equivalent to: bc 16,0,target)
  • Clear left immediate clrldi ra,rs,n (n < 64) rldicl ra,rs,0,n
  • CTR mtctr Rx mtspr 9,Rx
test_0_litex_bios_r1()

litex bios IMM64 macro test

test_0_litex_trampoline()
test_2_load_store()
test_30_addis()
test_31_addis()

tests for zero not in register zero

test_3_load_store()
test_add_with_carry()
test_addis()
test_crnand()
test_crnand_2()
test_crxor()
test_crxor_2()
test_data = []
test_example()
test_isel_1()
test_isel_2()
test_isel_3()
test_ld_rev_ext()
test_ldst()
test_ldst_extended()
test_ldst_update()
test_loop()

in godbolt.org: register unsigned long i asm (“r9”); void square(void) {

i = 16; do {

i = i - 1;

} while (i != 12);

}

test_mulli()
test_nop()
test_st_rev_ext()
test_sub()
test_zero_illegal()

openpower.simulator.test_trap_sim module

class openpower.simulator.test_trap_sim.TrapDecoderTestCase(name='div')

Bases: openpower.simulator.test_sim.DecoderBase, openpower.simulator.test_trap_sim.TrapSimTestCases

class openpower.simulator.test_trap_sim.TrapSimTestCases(name='div')

Bases: nmutil.formaltest.FHDLTestCase

run_tst_program(prog, initial_regs=None, initial_sprs=None, initial_mem=None)
test_0_not_twi()
test_1_twi_eq()
test_data = []

Module contents