soc.regfile package

Submodules

soc.regfile.regfile module

Specialist Regfiles

These are not “normal” binary-indexed regfiles (although that is included). They include unary indexed regfiles as well as Dependency-tracked ones (SPR files with 1024 registers, only around 4-5 of which need to be active) and special “split” regfiles that have 8R8W for 8 4-bit quantities and a 1R1W to read/write all 8 4-bit registers in a single one-off 32-bit way.

Due to the way that the Dependency Matrices are set up (bit-vectors), the primary focus here is on unary indexing.

Links:

class soc.regfile.regfile.RegFile(width, depth)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
ports()
read_port(name=None)
unary = False
write_port(name=None)
class soc.regfile.regfile.RegFileArray(width, depth, synced=True)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
ports()
read_port(name=None)
read_reg_port(name=None)
unary = True

an array-based register file (register having write-through capability) that has no “address” decoder, instead it has individual write-en and read-en signals (per port).

write_port(name=None)
write_reg_port(name=None)
class soc.regfile.regfile.RegFileMem(width, depth, fwd_bus_mode=False, synced=True)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
read_port(name=None)
unary = False
write_port(name=None)
class soc.regfile.regfile.Register(width, writethru=True, synced=True, resetval=0)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)
ports()
read_port(name=None)
write_port(name=None)
soc.regfile.regfile.ortreereduce(tree, attr='data_o')
soc.regfile.regfile.regfile_array_sim(dut, rp1, rp2, wp, wp2)
soc.regfile.regfile.regfile_sim(dut, rp, wp)
soc.regfile.regfile.test_regfile()

soc.regfile.regfiles module

POWER9 regfiles

Defines the following register files:

  • INT regfile - 32x 64-bit
  • SPR regfile - 110x 64-bit
  • CR regfile - CR0-7
  • XER regfile - XER.so, XER.ca/ca32, XER.ov/ov32
  • FAST regfile - CTR, LR, TAR, SRR1, SRR2
  • STATE regfile - PC, MSR, (SimpleV VL later)

Note: this should NOT have name conventions hard-coded (dedicated ports per regname). However it is convenient for now.

Links:

class soc.regfile.regfiles.CRRegs(svp64_en=False, regreduce_en=False)

Bases: soc.regfile.virtual_port.VirtualRegPort

Condition Code Registers (CR0-7)

  • QTY 8of 8-bit registers
  • 3R1W 4-bit-wide with additional 1R1W for the “full” 32-bit width
  • Array-based unary-indexed (not binary-indexed)
  • write-through capability (read on same cycle as write)
class soc.regfile.regfiles.FastRegs(svp64_en=False, regreduce_en=False)

Bases: soc.regfile.regfile.RegFileMem, openpower.consts.FastRegsEnum

FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC

  • QTY 6of 64-bit registers
  • 3R2W
  • Array-based unary-indexed (not binary-indexed)
  • write-through capability (read on same cycle as write)

Note: r/w issue are used by issuer to increment/decrement TB/DEC.

class soc.regfile.regfiles.IntRegs(svp64_en=False, regreduce_en=False)

Bases: soc.regfile.regfile.RegFileMem

  • QTY 32of 64-bit registers
  • 3R2W
  • Array-based unary-indexed (not binary-indexed)
  • write-through capability (read on same cycle as write)
class soc.regfile.regfiles.RegFiles(pspec)

Bases: object

elaborate_into(m, platform)
class soc.regfile.regfiles.SPRRegs(svp64_en=False, regreduce_en=False)

Bases: soc.regfile.regfile.RegFileMem

  • QTY len(SPRs) 64-bit registers
  • 1R1W
  • binary-indexed but REQUIRES MAPPING
  • write-through capability (read on same cycle as write)
class soc.regfile.regfiles.StateRegs(svp64_en=False, regreduce_en=False)

Bases: soc.regfile.regfile.RegFileArray, openpower.consts.StateRegsEnum

State regfile - PC, MSR, SVSTATE (for SimpleV)

  • QTY 3of 64-bit registers
  • 4R3W
  • Array-based unary-indexed (not binary-indexed)
  • write-through capability (read on same cycle as write)

Note: d_wr1 d_rd1 are for use by the decoder, to get at the PC. will probably have to also add one so it can get at the MSR as well. (d_rd2)

class soc.regfile.regfiles.XERRegs(svp64_en=False, regreduce_en=False)

Bases: soc.regfile.virtual_port.VirtualRegPort, openpower.consts.XERRegsEnum

XER Registers (SO, CA/CA32, OV/OV32)

  • QTY 3of 2-bit registers
  • 3R3W 2-bit-wide with additional 1R1W for the “full” 6-bit width
  • Array-based unary-indexed (not binary-indexed)
  • write-through capability (read on same cycle as write)
CA = 1
OV = 2
SO = 0

soc.regfile.util module

soc.regfile.util.fast_reg_to_spr(spr_num)
soc.regfile.util.slow_reg_to_spr(slow_reg)
soc.regfile.util.spr_to_fast_reg(spr_num)
soc.regfile.util.spr_to_slow_reg(spr_num)

soc.regfile.virtual_port module

VirtualRegPort - terrible name for a complex register class

This Register file has a “virtual” port on it which is effectively the ability to read and write to absolutely every bit in the regfile at once. This is achieved by having N actual read and write ports if there are N registers. That results in a staggeringly high gate count with full crossbars, so attempting to do use this for anything other than really small registers (XER, CR) is a seriously bad idea.

class soc.regfile.virtual_port.VirtualRegPort(bitwidth, n_regs, rd2=False)

Bases: soc.regfile.regfile.RegFileArray

connect_full_rd(m, rfull, name)
elaborate(platform)
soc.regfile.virtual_port.regfile_array_sim(dut, rp1, rp2, rp3, wp)
soc.regfile.virtual_port.test_regfile()

Module contents