soc.experiment.test package

Submodules

soc.experiment.test.async_sim module

class soc.experiment.test.async_sim.AsyncThing

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

class soc.experiment.test.async_sim.Domain1

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

class soc.experiment.test.async_sim.Domain2

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

soc.experiment.test.async_sim.async_sim(dut)

soc.experiment.test.async_sim.async_sim_clk(dut)

soc.experiment.test.async_sim.domain_sim(dut)

soc.experiment.test.test_compalu_fsm_multi module

Computation Unit (aka “ALU Manager”).

Manages a Pipeline or FSM, ensuring that the start and end time are 100% monitored. At no time may the ALU proceed without this module notifying the Dependency Matrices. At no time is a result production “abandoned”. This module blocks (indicates busy) starting from when it first receives an opcode until it receives notification that its result(s) have been successfully stored in the regfile(s)

Documented at http://libre-soc.org/3d_gpu/architecture/compunit

class soc.experiment.test.test_compalu_fsm_multi.CompUnitParallelTest(dut)

Bases: object

driver()

issue()

operation(a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0, rdmaskn=(0, 0))

rd(rd_idx)

run_simulation(vcd_name)

wr(wr_idx)

soc.experiment.test.test_compalu_fsm_multi.op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0)

soc.experiment.test.test_compalu_fsm_multi.scoreboard_sim(dut)

soc.experiment.test.test_compalu_fsm_multi.scoreboard_sim_dummy(dut)

soc.experiment.test.test_compalu_fsm_multi.test_compunit()

soc.experiment.test.test_compalu_fsm_multi.test_compunit_regspec1()

soc.experiment.test.test_compalu_fsm_multi.test_compunit_regspec3()

soc.experiment.test.test_compalu_multi module

Computation Unit (aka “ALU Manager”).

Manages a Pipeline or FSM, ensuring that the start and end time are 100% monitored. At no time may the ALU proceed without this module notifying the Dependency Matrices. At no time is a result production “abandoned”. This module blocks (indicates busy) starting from when it first receives an opcode until it receives notification that its result(s) have been successfully stored in the regfile(s)

Documented at http://libre-soc.org/3d_gpu/architecture/compunit

class soc.experiment.test.test_compalu_multi.OpSim(dut, sim)

Bases: object

ALU Operation issuer

Issues operations to the DUT

issue(src_i, op, expected, src_delays, dest_delays, inv_a=0, imm=0, imm_ok=0, zero_a=0, rc=0, rdmaskn=None, wrmask=None)

Executes the issue operation

class soc.experiment.test.test_compalu_multi.OperandProducer(sim, dut, op_index)

Bases: object

Produces an operand when requested by the Computation Unit (dut parameter), using the rel_o / go_i handshake.

Attaches itself to the dut operand indexed by op_index.

Has a programmable delay between the assertion of rel_o and the go_i pulse.

Data is presented only during the cycle in which go_i is active.

It adds itself as a passive process to the simulation (sim parameter). Since it is passive, it will not hang the simulation, and does not need a flag to terminate itself.

count = None

transaction counter

send(data, delay)

Schedules the module to send some data, counting delay cycles after rel_i becomes active.

To be called from the main test-bench process, it returns in the same cycle.

Communication with the worker process is done by means of combinatorial simulation-only signals.

class soc.experiment.test.test_compalu_multi.ResultConsumer(sim, dut, op_index)

Bases: object

Consumes a result when requested by the Computation Unit (dut parameter), using the rel_o / go_i handshake.

Attaches itself to the dut result indexed by op_index.

Has a programmable delay between the assertion of rel_o and the go_i pulse.

Data is retrieved only during the cycle in which go_i is active.

It adds itself as a passive process to the simulation (sim parameter). Since it is passive, it will not hang the simulation, and does not need a flag to terminate itself.

count = None

transaction counter

receive(expected, delay)

Schedules the module to receive some result, counting delay cycles after rel_i becomes active. As ‘go_i’ goes active, check the result with expected.

To be called from the main test-bench process, it returns in the same cycle.

Communication with the worker process is done by means of combinatorial simulation-only signals.

soc.experiment.test.test_compalu_multi.op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0)

soc.experiment.test.test_compalu_multi.scoreboard_sim(op)

soc.experiment.test.test_compalu_multi.scoreboard_sim_dummy(op)

soc.experiment.test.test_compalu_multi.scoreboard_sim_fsm(dut, producers, consumers)

soc.experiment.test.test_compalu_multi.test_compunit()

soc.experiment.test.test_compalu_multi.test_compunit_fsm()

soc.experiment.test.test_compalu_multi.test_compunit_regspec1()

soc.experiment.test.test_compalu_multi.test_compunit_regspec2_fsm()

soc.experiment.test.test_compalu_multi.test_compunit_regspec3()

soc.experiment.test.test_compalu_multi.wrap(process)

soc.experiment.test.test_l0_cache_buffer2 module

test cases for LDSTSplitter and L0CacheBuffer2

class soc.experiment.test.test_l0_cache_buffer2.TestCachedMemoryPortInterface(regwid=64, addrwid=4)

Bases: soc.experiment.pimem.PortInterfaceBase

TestCacheMemoryPortInterface

This is a test class for simple verification of LDSTSplitter conforming to PortInterface

elaborate(platform)

get_rd_data(m)

ports()

set_rd_addr(m, addr, mask)

set_wr_addr(m, addr, mask)

set_wr_data(m, data, wen)

soc.experiment.test.test_l0_cache_buffer2.test_cache_single()

soc.experiment.test.test_l0_cache_buffer2.test_cache_single_run(dut)

soc.experiment.test.test_mmu_dcache module

soc.experiment.test.test_mmu_dcache.b(x)

soc.experiment.test.test_mmu_dcache.icache_sim(dut, mem)

soc.experiment.test.test_mmu_dcache.mmu_lookup(mmu, addr)

soc.experiment.test.test_mmu_dcache.mmu_sim(mmu)

soc.experiment.test.test_mmu_dcache.set_stop(newval)

soc.experiment.test.test_mmu_dcache.test_icache()

soc.experiment.test.test_mmu_dcache.test_icache_il()

soc.experiment.test.test_mmu_dcache.test_mmu()

soc.experiment.test.test_mmu_dcache.wb_get(c, mem, name)

simulator process for getting memory load requests

soc.experiment.test.test_mmu_dcache_pi module

class soc.experiment.test.test_mmu_dcache_pi.TestMicrowattMemoryPortInterface(mmu, dcache, regwid=64, addrwid=4)

Bases: soc.experiment.pimem.PortInterfaceBase

This is a Test Class for MMU and DCache conforming to PortInterface

elaborate(platform)

get_rd_data(m)

ports()

set_rd_addr(m, addr, mask)

set_wr_addr(m, addr, mask)

set_wr_data(m, data, wen)

soc.experiment.test.test_mmu_dcache_pi.mmu_lookup(dut, addr)

soc.experiment.test.test_mmu_dcache_pi.mmu_sim(dut)

soc.experiment.test.test_mmu_dcache_pi.test_mmu()

soc.experiment.test.test_mmu_dcache_pi.wb_get(dc)

simulator process for getting memory load requests

Module contents