soc.bus package

Subpackages

• soc.bus.test package
  • Submodules
  • soc.bus.test.test_minerva module
  • soc.bus.test.test_sram_wb_downconvert module
  • soc.bus.test.test_sram_wishbone module
  • soc.bus.test.wb_rw module
  • Module contents

Submodules

soc.bus.SPBlock512W64B8W module

class soc.bus.SPBlock512W64B8W.SPBlock512W64B8W(bus=None, features=None, name=None)

Bases: nmigen.hdl.ir.Elaboratable

SRAM module carrying a volatile 4k memory block (implemented with Instance SPBlock512W64B8W). 512 rows, 64-bit, QTY 8 write-enable lines

elaborate(platform)

soc.bus.simple_gpio module

Simple GPIO peripheral on wishbone

This is an extremely simple GPIO peripheral intended for use in XICS testing, however it could also be used as an actual GPIO peripheral

class soc.bus.simple_gpio.SimpleGPIO(n_gpio=16)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

ports()

soc.bus.simple_gpio.read_gpio(gpio, addr)

soc.bus.simple_gpio.sim_gpio(gpio)

soc.bus.simple_gpio.test_gpio()

soc.bus.sram module

class soc.bus.sram.SRAM(memory, read_only=False, bus=None, granularity=None, features=None)

Bases: nmigen.hdl.ir.Elaboratable

SRAM module carrying a volatile memory block (implemented with Memory) that can be read and write (or only read if the SRAM is read-only) through a Wishbone bus.

If no Wishbone bus is specified during initialisation, this creates one whose address width is just enough to fit the whole memory (i.e. equals to the log2(memory depth) rounded up), and whose data width is equal to the memory width.

Parameters:

• memory (Memory) – The memory to be accessed via the Wishbone bus.
• read_only (bool) – Whether or not the memory is read-only. Defaults to False.
• bus (Interface or None) – The Wishbone bus interface providing access to the read/write ports of the memory. Optional and defaults to None, which lets this module to instantiate one as described above, having the granularity, features and alignment as specified by their corresponding parameters.
• granularity (int or None) – If the Wishbone bus is not specified, this is the granularity of the Wishbone bus. Optional. See Interface.
• features (iter(str)) – If the Wishbone bus is not specified, this is the optional signal set for the Wishbone bus. See Interface.

memory

Memory – The memory to be accessed via the Wishbone bus.

bus

Interface – The Wishbone bus interface providing access to the read/write ports of the memory.

elaborate(platform)

soc.bus.wb_downconvert module

class soc.bus.wb_downconvert.WishboneDownConvert(master, slave)

Bases: nmigen.hdl.ir.Elaboratable

DownConverter

This module splits Wishbone accesses from a master interface to a smaller slave interface.

Writes:

Writes from master are split N writes to the slave. Access is acked when the last access is acked by the slave.

Reads:

Read from master are split in N reads to the the slave. Read data from the slave are cached before being presented, concatenated on the last access.

Todo

Manage err signal? (Not implemented since we generally don’t use it on Migen/MiSoC modules)

elaborate(platform)

Module contents