soc.bus.test package¶
Submodules¶
soc.bus.test.test_minerva module¶
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class
soc.bus.test.test_minerva.TestSRAMBareFetchUnit(pspec)¶ Bases:
soc.minerva.units.fetch.BareFetchUnit-
elaborate(platform)¶
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class
soc.bus.test.test_minerva.TestSRAMBareLoadStoreUnit(pspec)¶ Bases:
soc.minerva.units.loadstore.BareLoadStoreUnit-
elaborate(platform)¶
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soc.bus.test.test_sram_wb_downconvert module¶
soc.bus.test.test_sram_wishbone module¶
demonstration of nmigen-soc SRAM behind a wishbone bus Bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=382
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soc.bus.test.test_sram_wishbone.print_sig(sig, format=None)¶
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soc.bus.test.test_sram_wishbone.process()¶
soc.bus.test.wb_rw module¶
Wishbone read/write utility routines
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soc.bus.test.wb_rw.wb_read(bus, addr, sel=True)¶
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soc.bus.test.wb_rw.wb_write(bus, addr, data, sel=True)¶