soc.memory_pipe_experiment package¶

Submodules¶

soc.memory_pipe_experiment.config module¶

class soc.memory_pipe_experiment.config.MemoryPipeConfig(*, bytes_per_cache_line=32, l1_way_count=8, l1_set_count=64, fu_op_id_shape=range(0, 32), fu_op_id_nop_value=0, physical_address_bits=48, memory_queue_chunk_size=4, memory_queue_entry_count=8)¶

Bases: object

bits_per_cache_line¶

l1_byte_count¶

l1_line_count¶

memory_queue_chunk_count¶

memory_queue_chunk_entries_end_index(chunk_index)¶: one past the end entry index for in the chunk chunk_index.

memory_queue_chunk_entries_start_index(chunk_index)¶: entry index of the first memory queue entry in the chunk chunk_index.

memory_queue_entry_index(chunk_index, index_in_chunk)¶

soc.memory_pipe_experiment.l1_cache_memory module¶

class soc.memory_pipe_experiment.l1_cache_memory.L1CacheMemory(config: soc.memory_pipe_experiment.config.MemoryPipeConfig)¶

Bases: nmigen.hdl.ir.Elaboratable

The data memory for the L1 cache.

It is conceptually organized into config.l1_way_count ways, where each way has config.l1_sets_count sets, where each set is a single cache line of config.bytes_per_cache_line bytes. None of the dimensions must be powers of 2, but must all be at least 1.

The memory has a single R/W port that can read or write (but not both) an entire cache line each cycle. When writing, writing to each byte can individually be enabled by setting the corresponding bit in write_byte_en.

The results of reading are available after the next clock edge.

The address is divided into set_index and way_index.

Parameters:

config: MemoryPipeConfig: The configuration.

Attributes:

config: MemoryPipeConfig: The configuration.
set_index: Signal(range(config.l1_set_count)): The input index of the set to read/write.
way_index: Signal(range(config.l1_way_count)): The input index of the way to read/write.
write_byte_en: Signal(config.bytes_per_cache_line): The per-byte write enable inputs.
write_enable: Signal(): The overall write enable input. Set to 1 to write and to 0 to read.
read_data: Signal(config.bits_per_cache_line): The read data output.
write_data: Signal(config.bits_per_cache_line): The write data input.

elaborate(platform)¶

soc.memory_pipe_experiment.memory_op module¶

class soc.memory_pipe_experiment.memory_op.MemoryOpData(config: soc.memory_pipe_experiment.config.MemoryPipeConfig)¶

Bases: nmutil.iocontrol.Object

eq_empty()¶: assign self to the canonical empty value.

is_empty¶

class soc.memory_pipe_experiment.memory_op.MemoryOpKind¶

Bases: enum.IntEnum

An enumeration.

AMO = 4¶

Fence = 1¶

LoadLinked = 5¶

Read = 2¶

StoreConditional = 6¶

Write = 3¶

soc.memory_pipe_experiment.memory_pipe module¶

class soc.memory_pipe_experiment.memory_pipe.MemoryPipe(config: soc.memory_pipe_experiment.config.MemoryPipeConfig)¶

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)¶

soc.memory_pipe_experiment.memory_queue module¶

class soc.memory_pipe_experiment.memory_queue.MemoryQueue(config: soc.memory_pipe_experiment.config.MemoryPipeConfig)¶

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)¶

class soc.memory_pipe_experiment.memory_queue.MemoryQueueChunk(config: soc.memory_pipe_experiment.config.MemoryPipeConfig, chunk_index: int)¶

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)¶

soc.memory_pipe_experiment.memory_queue_entry module¶

class soc.memory_pipe_experiment.memory_queue_entry.MemoryQueueEntry(config: soc.memory_pipe_experiment.config.MemoryPipeConfig)¶

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)¶

next_op = None¶: next_op of corresponding memory queue entry in the next chunk towards the back of the queue.

class soc.memory_pipe_experiment.memory_queue_entry.MemoryQueueEntryComb(config: soc.memory_pipe_experiment.config.MemoryPipeConfig)¶

Bases: nmigen.hdl.ir.Elaboratable

Combinatorial state calculation for a memory queue entry, without shifting.

elaborate(platform)¶

soc.memory_pipe_experiment.test_config module¶

soc.memory_pipe_experiment.test_l1_cache_memory module¶

class soc.memory_pipe_experiment.test_l1_cache_memory.TestL1CacheMemory(methodName='runTest')¶

Bases: unittest.case.TestCase

test_l1_cache_memory()¶

soc.memory_pipe_experiment package¶

Submodules¶

soc.memory_pipe_experiment.config module¶

soc.memory_pipe_experiment.l1_cache_memory module¶

soc.memory_pipe_experiment.memory_op module¶

soc.memory_pipe_experiment.memory_pipe module¶

soc.memory_pipe_experiment.memory_queue module¶

soc.memory_pipe_experiment.memory_queue_entry module¶

soc.memory_pipe_experiment.test_config module¶

soc.memory_pipe_experiment.test_l1_cache_memory module¶

soc.memory_pipe_experiment.test_memory_op module¶

soc.memory_pipe_experiment.test_memory_pipe module¶

soc.memory_pipe_experiment.test_memory_queue module¶

soc.memory_pipe_experiment.test_memory_queue_entry module¶

Module contents¶