soc.interrupts package¶
Submodules¶
soc.interrupts.xics module¶
Microwatt xics.vhdl converted to nmigen # # This is a simple XICS compliant interrupt controller. This is a # Presenter (ICP) and Source (ICS) in two small units directly # connected to each other with no routing layer. # # The sources have a configurable IRQ priority set a set of ICS # registers in the source units. # # The source ids start at 16 for int_level_in(0) and go up from # there (ie int_level_in(1) is source id 17). XXX Make a generic # # The presentation layer will pick an interupt that is more # favourable than the current CPPR and present it via the XISR and # send an interrpt to the processor (via e_out). This may not be the # highest priority interrupt currently presented (which is allowed # via XICS) #
-
class
soc.interrupts.xics.ICS2ICP(name)¶ Bases:
nmutil.iocontrol.RecordObject# Level interrupts only, ICS just keeps prsenting the # highest priority interrupt. Once handling edge, something # smarter involving handshake & reject support will be needed
-
class
soc.interrupts.xics.RegInternal(name=None)¶ Bases:
nmutil.iocontrol.RecordObject
-
class
soc.interrupts.xics.XICS_ICS(SRC_NUM=16, PRIO_BITS=8)¶ Bases:
nmigen.hdl.ir.Elaboratable-
a_mf_b(a, b)¶
-
elaborate(platform)¶
-
ports()¶
-
prio_pack(pri8)¶
-
prio_unpack(pri)¶
-
-
class
soc.interrupts.xics.Xive(name, wid, rst)¶ Bases:
nmutil.iocontrol.RecordObject
-
soc.interrupts.xics.bswap(v)¶
-
soc.interrupts.xics.get_field(x, wid, shift)¶
-
soc.interrupts.xics.sim_xics(icp, ics)¶
-
soc.interrupts.xics.sim_xics_icp(dut)¶
-
soc.interrupts.xics.swap32(x)¶
-
soc.interrupts.xics.test_xics()¶
-
soc.interrupts.xics.test_xics_icp()¶
-
soc.interrupts.xics.test_xics_ics()¶