soc.decoder package

Subpackages

• soc.decoder.formal package
  • Submodules
  • soc.decoder.formal.proof_decoder module
  • soc.decoder.formal.proof_decoder2 module
  • Module contents
• soc.decoder.isa package
  • Submodules
  • soc.decoder.isa.caller module
  • soc.decoder.isa.mem module
  • soc.decoder.isa.radixmmu module
  • soc.decoder.isa.test_caller module
  • Module contents
• soc.decoder.isa2 package
  • Submodules
  • soc.decoder.isa2.all module
  • soc.decoder.isa2.bcd module
  • soc.decoder.isa2.branch module
  • soc.decoder.isa2.caller module
  • soc.decoder.isa2.comparefixed module
  • soc.decoder.isa2.condition module
  • soc.decoder.isa2.fixedarith module
  • soc.decoder.isa2.fixedldstcache module
  • soc.decoder.isa2.fixedload module
  • soc.decoder.isa2.fixedlogical module
  • soc.decoder.isa2.fixedshift module
  • soc.decoder.isa2.fixedstore module
  • soc.decoder.isa2.fixedtrap module
  • soc.decoder.isa2.sprset module
  • soc.decoder.isa2.stringldst module
  • soc.decoder.isa2.system module
  • soc.decoder.isa2.test_caller module
  • Module contents

Submodules

soc.decoder.astPrinter module

soc.decoder.decode2execute1 module

soc.decoder.helpers module

soc.decoder.helpers.EXTS(value)

extends sign bit out from current MSB to all 256 bits

soc.decoder.helpers.EXTS128(value)

extends sign bit out from current MSB to 128 bits

soc.decoder.helpers.EXTS64(value)

extends sign bit out from current MSB to 64 bits

soc.decoder.helpers.EXTZ64(value)

class soc.decoder.helpers.HelperTests(methodName='runTest')

Bases: unittest.case.TestCase

assertHex(a, b)

test_EXTS64()

test_MASK()

test_ROTL32()

test_ROTL64()

soc.decoder.helpers.MASK(x, y)

soc.decoder.helpers.MODS(n, d)

Links: * https://bugs.libre-soc.org/show_bug.cgi?id=324 - add trunc_div and trunc_rem

soc.decoder.helpers.MULS(a, b)

soc.decoder.helpers.ROTL32(value, bits)

soc.decoder.helpers.ROTL64(value, bits)

soc.decoder.helpers.eq(a, b)

soc.decoder.helpers.exts(value, bits)

soc.decoder.helpers.ge(a, b)

soc.decoder.helpers.gt(a, b)

soc.decoder.helpers.le(a, b)

soc.decoder.helpers.length(a)

soc.decoder.helpers.lt(a, b)

soc.decoder.helpers.ne(a, b)

soc.decoder.helpers.rotl(value, bits, wordlen)

soc.decoder.helpers.undefined(v)

function that, for Power spec purposes, returns undefined bits of the same shape as the input bits. however, for purposes of matching POWER9’s behavior returns the input bits unchanged. this effectively “marks” (tags) locations in the v3.0B spec that need to be submitted for clarification.

soc.decoder.orderedset module

class soc.decoder.orderedset.OrderedSet(iterable=None)

Bases: collections.abc.MutableSet

add(key)

Add an element.

discard(key)

Remove an element. Do not raise an exception if absent.

soc.decoder.power_decoder module

soc.decoder.power_decoder2 module

soc.decoder.power_enums module

soc.decoder.power_fields module

soc.decoder.power_fieldsn module

soc.decoder.power_regspec_map module

regspec_decode

functions for the relationship between regspecs and Decode2Execute1Type

these functions encodes the understanding (relationship) between Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2).

based on the regspec, which contains the register file name and register name, return a tuple of:

• how the decoder should determine whether the Function Unit needs access to a given Regport or not
• which Regfile number on that port should be read to get that data
• when it comes to writing: likewise, which Regfile num should be written

Note that some of the port numbering encoding is unary. in the case of “Full Condition Register”, it’s a full 8-bit mask of read/write-enables. This actually matches directly with the XFX field in MTCR, and at some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO).

For the INT and CR numbering, these are expressed in binary in the instruction and need to be converted to unary (1<<read_reg1.data). Note however that XFX in MTCR is unary-masked!

XER regs are implicitly-encoded (hard-coded) based on whether the operation has carry or overflow.

FAST regfile is, again, implicitly encoded, back in PowerDecode2, based on the type of operation (see DecodeB for an example, where fast_out is set, then carried into read_fast2 in PowerDecode2).

The SPR regfile on the other hand is binary-encoded, and, furthermore, has to be “remapped” to internal SPR Enum indices (see SPRMap in PowerDecode2) see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs

soc.decoder.power_regspec_map.regspec_decode_read(e, regfile, name)

soc.decoder.power_regspec_map.regspec_decode_write(e, regfile, name)

soc.decoder.selectable_int module

Module contents