soc.debug package

Submodules

soc.debug.dmi module

Converted from microwatt core_debug.vhdl to nmigen

Provides a DMI (Debug Module Interface) for accessing a Libre-SOC core, compatible with microwatt’s same interface.

See constants below for addresses and register formats

class soc.debug.dmi.CoreDebug(LOG_LENGTH=0)

Bases: nmigen.hdl.ir.Elaboratable

elaborate(platform)

ports()

class soc.debug.dmi.DBGCore

Bases: object

CR = 8

CTRL = 0

GSPR_DATA = 5

GSPR_IDX = 4

LOG_ADDR = 6

LOG_DATA = 7

MSR = 3

NIA = 2

STAT = 1

SVSTATE = 10

XER = 9

class soc.debug.dmi.DBGCtrl

Bases: object

ICRESET = 2

RESET = 1

START = 4

STEP = 3

STOP = 0

class soc.debug.dmi.DBGStat

Bases: object

STOPPED = 1

STOPPING = 0

TERM = 2

class soc.debug.dmi.DMIInterface(name=None)

Bases: nmutil.iocontrol.RecordObject

connect_to(other)

class soc.debug.dmi.DbgCRReg(name)

Bases: nmutil.iocontrol.RecordObject

class soc.debug.dmi.DbgReg(name)

Bases: nmutil.iocontrol.RecordObject

soc.debug.dmi.test_debug()

soc.debug.dmi2jtag module

DMI 2 JTAG

based on Staf Verhaegen (Chips4Makers) wishbone TAP

class soc.debug.dmi2jtag.DMITAP(*, with_reset=False, ir_width=None, manufacturer_id=(const 11'd1151), part_number=(const 16'd1), version=(const 4'd0), name=None, src_loc_at=0)

Bases: c4m.nmigen.jtag.tap.TAP

external_ports()

soc.debug.firmware_upload module

JTAG Wishbone firmware upload program

to test, run “python3 debug/test/test_jtag_tap_srv.py server”

soc.debug.firmware_upload.brev(n, width)

soc.debug.firmware_upload.jtag_sim(dut, firmware)

uploads firmware with the following commands: * read IDcode (to check) * set “stopped” and reset * repeat until confirmed “stopped” * upload data over wishbone * read data back and check it * issue cache flush command * issue “start” command

soc.debug.firmware_upload.read_dmi_addr(dut, dmi_addr)

soc.debug.firmware_upload.test_pinset()

soc.debug.firmware_upload.writeread_dmi_addr(dut, dmi_addr, data)

soc.debug.jtag module

JTAG interface

using Staf Verhaegen (Chips4Makers) wishbone TAP

class soc.debug.jtag.JTAG(pinset, wb_data_wid=32)

Bases: soc.debug.dmi2jtag.DMITAP, soc.debug.jtag.Pins

elaborate(platform)

external_ports()

create a list of ports that goes into the top level il (or verilog)

class soc.debug.jtag.Pins(pindict)

Bases: object

declare a list of pins, including name and direction. grouped by fn the pin dictionary needs to be in a reliable order so that the JTAG Boundary Scan is also in a reliable order

soc.debug.jtag.dummy_pinset()

soc.debug.jtagutils module

class soc.debug.jtagutils.JTAGClient(debug=False)

Bases: object

close()

get_data(length=1024, timeout=None)

jtagremote_client_recv(timeout=None)

jtagremote_client_send(to_send)

send(data)

class soc.debug.jtagutils.JTAGServer(debug=False)

Bases: object

close()

get_connection(timeout=0)

get_data(length=1024, timeout=None)

jtagremote_server_recv(tdo)

send(data)

soc.debug.jtagutils.client_sync(dut)

soc.debug.jtagutils.get_data(s, length=1024, timeout=None)

soc.debug.jtagutils.jtag_read_write_reg(dut, addr, d_len, d_in=0)

soc.debug.jtagutils.jtag_set_get_dr(dut, d_len, d_in=0)

soc.debug.jtagutils.jtag_set_idle(dut)

soc.debug.jtagutils.jtag_set_ir(dut, addr)

soc.debug.jtagutils.jtag_set_reset(dut)

soc.debug.jtagutils.jtag_set_run(dut)

soc.debug.jtagutils.jtag_set_shift_dr(dut)

soc.debug.jtagutils.jtag_set_shift_ir(dut)

soc.debug.jtagutils.jtag_srv(dut)

soc.debug.jtagutils.tms_data_getset(dut, tms, d_len, d_in=0)

soc.debug.jtagutils.tms_state_set(dut, bits)

soc.debug.ls180_pins module

Module contents