ieee754.fpdiv package

Subpackages

• ieee754.fpdiv.test package
  • Submodules
  • ieee754.fpdiv.test.div_data16 module
  • ieee754.fpdiv.test.div_data32 module
  • ieee754.fpdiv.test.sqrt_data16 module
  • ieee754.fpdiv.test.sqrt_data32 module
  • ieee754.fpdiv.test.test_fpdiv_pipe module
  • ieee754.fpdiv.test.test_fpdiv_pipe_16 module
  • ieee754.fpdiv.test.test_fpdiv_pipe_32 module
  • ieee754.fpdiv.test.test_fprsqrt_pipe module
  • ieee754.fpdiv.test.test_fprsqrt_pipe_16 module
  • ieee754.fpdiv.test.test_fprsqrt_pipe_32 module
  • ieee754.fpdiv.test.test_fpsqrt_pipe module
  • ieee754.fpdiv.test.test_fpsqrt_pipe_16 module
  • ieee754.fpdiv.test.test_fpsqrt_pipe_32 module
  • ieee754.fpdiv.test.test_fpsqrt_pipe_64 module
  • Module contents

Submodules

ieee754.fpdiv.div0 module

IEEE754 Floating Point Divider / Square-Root / Reciprocal-Square-Root

Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net> Copyright (C) 2019 Jacob Lifshay

Relevant bugreports: * http://bugs.libre-riscv.org/show_bug.cgi?id=99 * http://bugs.libre-riscv.org/show_bug.cgi?id=43 * http://bugs.libre-riscv.org/show_bug.cgi?id=44

class ieee754.fpdiv.div0.FPDivPreFPAdjust(pspec)

Bases: nmutil.pipemodbase.PipeModBase

DIV/SQRT/RSQRT “preparation” module.

adjusts mantissa and exponent (sqrt/rsqrt exponent must be even), puts exponent (and sign) into data structures for passing through to the end, and puts the (adjusted) mantissa into the processing engine.

no actual processing occurs here: it is purely preparation work.

elaborate(platform)

ispec()

ospec()

ieee754.fpdiv.div2 module

IEEE Floating Point Divider

Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net> Copyright (C) 2019 Jacob Lifshay

Relevant bugreports: * http://bugs.libre-riscv.org/show_bug.cgi?id=99 * http://bugs.libre-riscv.org/show_bug.cgi?id=43 * http://bugs.libre-riscv.org/show_bug.cgi?id=44

class ieee754.fpdiv.div2.FPDivPostToFPFormat(pspec)

Bases: nmutil.pipemodbase.PipeModBase

Last stage of div: preparation for normalisation.

NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY does “conversion” out of the Q/REM last stage

elaborate(platform)

ispec()

ospec()

ieee754.fpdiv.divstages module

IEEE754 Floating Point pipelined Divider

This module simply constructs register-based pipeline(s) out of appropriate combinatorial blocks: setup, intermediary and final single-clock pipelines.

“actual” processing is carried out by the DivPipeCalculateStage combinatorial block: everything else is chaining and pre- and post- data formatting.

there’s no “actual” work done here: it’s just a “joining-together” job. see pipeline.py for an ASCII diagram showing how everything fits together

Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99

class ieee754.fpdiv.divstages.FPDivStagesFinal(pspec, n_stages, stage_offs)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

gets module chain

note: this is a pure combinatorial module (StageChain). therefore each sub-module must also be combinatorial

class ieee754.fpdiv.divstages.FPDivStagesIntermediate(pspec, n_stages, stage_offs)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

gets module chain

note: this is a pure combinatorial module (StageChain). therefore each sub-module must also be combinatorial

class ieee754.fpdiv.divstages.FPDivStagesSetup(pspec, n_stages, stage_offs)

Bases: nmutil.pipemodbase.PipeModBaseChain

get_chain()

gets module chain

note: this is a pure combinatorial module (StageChain). therefore each sub-module must also be combinatorial

ieee754.fpdiv.op module

DivPipeOp enum for all operations the division pipeline can execute

class ieee754.fpdiv.op.DivPipeOp

Bases: enum.IntEnum

The enumeration of operations that the division pipeline can execute

Integer division and remainder use truncating division (quotient rounded towards zero – the standard for Rust and C/C++) rather than Python’s standard flooring division (quotient rounded towards negative infinity). This means that signed integer remainder takes its sign from the dividend instead of the divisor.

DivS32 = 8

Signed 32-bit Integer by 32-bit producing 32-bit quotient.

quotient = i32(i32(dividend) / i32(divisor))

Power instruction: divw RV64 instruction: divw

DivS32High = 6

Signed 32-bit integer shifted left by 32-bits divided by 32-bit integer producing 32-bit integer quotient.

quotient = i32((i32(dividend) << 32) / i32(divisor))

Power instruction: divwe

DivS64 = 2

Signed 64-bit Integer by 64-bit producing 64-bit quotient.

quotient = i64(i64(dividend) / i64(divisor))

Power instruction: divd RV64 instruction: div

DivS64High = 0

Signed 64-bit integer shifted left by 64-bits divided by 64-bit integer producing 64-bit integer quotient.

quotient = i64((i64(dividend) << 64) / i64(divisor))

Power instruction: divde

DivU32 = 9

Signed 32-bit Integer by 32-bit producing 32-bit quotient.

quotient = i32(i32(dividend) / i32(divisor))

Power instruction: divwu RV64 instruction: divuw

DivU32High = 7

Unsigned 32-bit Integer shifted left by 32-bits by 32-bit producing 32-bit quotient.

quotient = u32((u32(dividend) << 32) / u32(divisor))

Power instruction: divweu

DivU64 = 3

Signed 64-bit Integer by 64-bit producing 64-bit quotient.

quotient = i64(i64(dividend) / i64(divisor))

Power instruction: divdu RV64 instruction: divu

DivU64High = 1

Unsigned 64-bit Integer shifted left by 64-bits by 64-bit producing 64-bit quotient.

quotient = u64((u64(dividend) << 64) / u64(divisor))

Power instruction: divdeu

RemS32 = 10

Signed 32-bit Integer by 32-bit producing 32-bit remainder.

remainder = i32(i32(dividend) % i32(divisor))

Power instruction: modsw RV64 instruction: remw

RemS64 = 4

Signed 64-bit Integer by 64-bit producing 64-bit remainder.

remainder = i64(i64(dividend) % i64(divisor))

Power instruction: modsd RV64 instruction: rem

RemU32 = 11

Unsigned 32-bit Integer by 32-bit producing 32-bit remainder.

remainder = u32(u32(dividend) % u32(divisor))

Power instruction: moduw RV64 instruction: remuw

RemU64 = 5

Unsigned 64-bit Integer by 64-bit producing 64-bit remainder.

remainder = u64(u64(dividend) % u64(divisor))

Power instruction: modud RV64 instruction: remu

ieee754.fpdiv.pipeline module

IEEE754 Floating Point Divider Pipeline

Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net> Copyright (C) 2019 Jacob Lifshay

Relevant bugreports: * http://bugs.libre-riscv.org/show_bug.cgi?id=99 * http://bugs.libre-riscv.org/show_bug.cgi?id=43 * http://bugs.libre-riscv.org/show_bug.cgi?id=44

Stack looks like this:

scnorm - FPDIVSpecialCasesDeNorm ispec FPBaseData —— ospec FPSCData

StageChain: FPDIVSpecialCasesMod,

FPAddDeNormMod

pipediv0 - FPDivStagesSetup ispec FPSCData ——– ospec DivPipeInterstageData

StageChain: FPDivPreFPAdjust,

DivPipeSetupStage, DivPipeCalculateStage, … DivPipeCalculateStage

pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData ——– ospec DivPipeInterstageData

StageChain: DivPipeCalculateStage,

… DivPipeCalculateStage

…

pipediv5 - FPDivStageFinal ispec FPDivStage0Data ——– ospec FPPostCalcData

StageChain: DivPipeCalculateStage,

… DivPipeCalculateStage, DivPipeFinalStage, FPDivPostToFPFormat

normpack - FPNormToPack ispec FPPostCalcData ——– ospec FPPackData

StageChain: Norm1ModSingle,

RoundMod, CorrectionsMod, PackMod

the number of combinatorial StageChains (n_comb_stages) in FPDivStages is an argument arranged to get the length of the whole pipeline down to sane numbers. it specifies the number of “blocks” that will be combinatorially chained together.

the reason for keeping the number of stages down is that for every pipeline clock delay, a corresponding ReservationStation is needed. if there are 24 pipeline stages, we need a whopping TWENTY FOUR RS’s. that’s far too many. 6 is just about an acceptable number. even 8 is starting to get alarmingly high.

class ieee754.fpdiv.pipeline.FPDIVBasePipe(pspec)

Bases: nmutil.singlepipe.ControlBase

elaborate(platform)

handles case where stage has dynamic ready/valid functions

class ieee754.fpdiv.pipeline.FPDIVMuxInOut(width, num_rows, op_wid=2)

Bases: nmutil.concurrentunit.ReservationStations

Reservation-Station version of FPDIV pipeline.

• fan-in on inputs (an array of FPBaseData: a,b,mid)
• N-stage divider pipeline
• fan-out on outputs (an array of FPPackData: z,mid)

Fan-in and Fan-out are combinatorial.

Op_wid:

• set this to the width of an operator which can

then be used to change the behaviour of the pipeline.

ieee754.fpdiv.pipeline.roundup(x, mod)

ieee754.fpdiv.specialcases module

IEEE Floating Point Divider

Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net> Copyright (C) 2019 Jacob Lifshay

Relevant bugreports: * http://bugs.libre-riscv.org/show_bug.cgi?id=99 * http://bugs.libre-riscv.org/show_bug.cgi?id=43 * http://bugs.libre-riscv.org/show_bug.cgi?id=44

class ieee754.fpdiv.specialcases.FPDIVSpecialCasesDeNorm(pspec)

Bases: nmutil.pipemodbase.PipeModBaseChain

special cases: NaNs, infs, zeros, denormalised

get_chain()

links module to inputs and outputs

class ieee754.fpdiv.specialcases.FPDIVSpecialCasesMod(pspec)

Bases: nmutil.pipemodbase.PipeModBase

special cases: NaNs, infs, zeros, denormalised see “Special Operations” https://steve.hollasch.net/cgindex/coding/ieeefloat.html

elaborate(platform)

ispec()

ospec()

Module contents