ieee754.fpadd package¶
Subpackages¶
- ieee754.fpadd.test package
- Submodules
- ieee754.fpadd.test.add_data16 module
- ieee754.fpadd.test.add_data32 module
- ieee754.fpadd.test.add_data64 module
- ieee754.fpadd.test.test_add module
- ieee754.fpadd.test.test_add16 module
- ieee754.fpadd.test.test_add64 module
- ieee754.fpadd.test.test_add_base module
- ieee754.fpadd.test.test_fpadd_pipe module
- ieee754.fpadd.test.test_fpadd_pipe_16 module
- ieee754.fpadd.test.test_fpadd_pipe_32 module
- ieee754.fpadd.test.test_fpadd_pipe_64 module
- Module contents
Submodules¶
ieee754.fpadd.add0 module¶
IEEE754 Floating Point Adder Pipeline
Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
ieee754.fpadd.add1 module¶
IEEE754 Floating Point Multiplier Pipeline
Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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class
ieee754.fpadd.add1.
FPAddStage1Mod
(pspec)¶ Bases:
nmutil.pipemodbase.PipeModBase
Second stage of add: preparation for normalisation. detects when tot sum is too big (tot[27] is kinda a carry bit)
if sum is too big (MSB is set), the mantissa needs shifting down and the exponent increased by 1.
we also need to extract the overflow info: sticky “accumulates” the bottom 2 LSBs if the shift occurs.
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elaborate
(platform)¶
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ispec
()¶
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ospec
()¶
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ieee754.fpadd.addstages module¶
IEEE754 Floating Point Adder Pipeline
Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
ieee754.fpadd.align module¶
IEEE754 Floating Point Library
Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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class
ieee754.fpadd.align.
FPAddAlignMultiMod
(width)¶ Bases:
object
Module to do mantissa alignment shift in multiple cycles
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elaborate
(platform)¶
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class
ieee754.fpadd.align.
FPAddAlignSingleMod
(pspec)¶ Bases:
nmutil.pipemodbase.PipeModBase
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elaborate
(platform)¶ Aligns A against B or B against A, depending on which has the greater exponent. This is done in a single cycle using variable-width bit-shift
the shifter used here is quite expensive in terms of gates. Mux A or B in (and out) into temporaries, as only one of them needs to be aligned against the other.
code is therefore slightly complex because after testing which exponent is greater, a and b get mux-routed into the multi-shifter and so does the output.
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ispec
()¶
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ospec
()¶
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ieee754.fpadd.datastruct module¶
IEEE754 Floating Point Adder Pipeline
Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
ieee754.fpadd.fadd_state module¶
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class
ieee754.fpadd.fadd_state.
FPADD
(width, single_cycle=False)¶ Bases:
ieee754.fpcommon.fpbase.FPBase
,nmigen.hdl.ir.Elaboratable
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elaborate
(platform=None)¶ creates the HDL code-fragment for FPAdd
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ieee754.fpadd.nmigen_add_experiment module¶
ieee754.fpadd.pipeline module¶
IEEE Floating Point Adder Pipeline
Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=75
Stack looks like this:
- scnorm - FPMulSpecialCasesDeNorm
- addalign - FPAddAlignSingleAdd
- normpack - FPNormToPack
scnorm - FPDIVSpecialCasesDeNorm ispec FPBaseData —— ospec FPSCData
- StageChain: FPMULSpecialCasesMod,
- FPAddDeNormMod FPAlignModSingle
addalign - FPAddAlignSingleAdd ispec FPSCData ——– ospec FPPostCalcData
- StageChain: FPAddAlignSingleMod
- FPAddStage0Mod FPAddStage1Mod
normpack - FPNormToPack ispec FPPostCalcData ——– ospec FPPackData
- StageChain: Norm1ModSingle,
- RoundMod, CorrectionsMod, PackMod
This pipeline has a 3 clock latency, and, with the separation into separate “modules”, it is quite clear how to create longer-latency pipelines (if needed) - just create a new, longer top-level (FPADDBasePipe alternative) and construct shorter pipe stages using the building blocks, RoundMod, FPAddStage0Mod etc.
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class
ieee754.fpadd.pipeline.
FPADDBasePipe
(pspec)¶ Bases:
nmutil.singlepipe.ControlBase
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elaborate
(platform)¶ handles case where stage has dynamic ready/valid functions
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class
ieee754.fpadd.pipeline.
FPADDMuxInOut
(width, num_rows, op_wid=None)¶ Bases:
nmutil.concurrentunit.ReservationStations
Reservation-Station version of FPADD pipeline.
- fan-in on inputs (an array of FPBaseData: a,b,mid)
- 3-stage adder pipeline
- fan-out on outputs (an array of FPPackData: z,mid)
Fan-in and Fan-out are combinatorial.
ieee754.fpadd.specialcases module¶
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class
ieee754.fpadd.specialcases.
FPAddSpecialCasesDeNorm
(pspec)¶ Bases:
nmutil.pipemodbase.PipeModBaseChain
special cases chain
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get_chain
()¶ links module to inputs and outputs
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class
ieee754.fpadd.specialcases.
FPAddSpecialCasesMod
(pspec)¶ Bases:
nmutil.pipemodbase.PipeModBase
special cases: NaNs, infs, zeros, denormalised NOTE: some of these are unique to add. see “Special Operations” https://steve.hollasch.net/cgindex/coding/ieeefloat.html
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elaborate
(platform)¶
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ispec
()¶
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ospec
()¶
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